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Activity

From 03/07/2018 to 04/05/2018

04/05/2018

01:04 AM Issue #1294 (Resolved): Connecting the wrong interface to a port does not cause an error
Good stuff! Thanks.
Merged into git towards 3.924.
Wilson Snyder

04/02/2018

06:21 PM Issue #1294: Connecting the wrong interface to a port does not cause an error
I think the latest commit takes care of everything:
https://github.com/toddstrader/verilator-dev/tree/wrong_intf
Todd Strader

04/01/2018

11:52 AM Issue #1297 (Duplicate): 1 Bit signed values
This was reported by another user last week, and is already fixed in the git version (but not released yet).
Thank...
Wilson Snyder
05:46 AM Issue #1297 (Duplicate): 1 Bit signed values
For example having the port: "input signed a" will lead to the following error:
syntax error, unexpected IDENTIFIE...
Kevin Townsend

03/30/2018

06:32 AM Issue #1296: SystemVerilog logic array inside struct should warn on bad index
Wilson Snyder wrote:
> No.
>
> logic [31:20] imm;
> $display("instr.imm[11]: %d <-- should be 1 ...
Sergi Granell
12:35 AM Issue #1296 (Feature): SystemVerilog logic array inside struct should warn on bad index
No.
logic [31:20] imm;
$display("instr.imm[11]: %d <-- should be 1 !!", instr.imm[11]);
Imm is...
Wilson Snyder

03/29/2018

11:27 PM Issue #1296 (NoFixNeeded): SystemVerilog logic array inside struct should warn on bad index
It looks like when you have a logic array inside a struct, and you try to access a bit of that field directly, they i... Sergi Granell
08:52 PM Issue #1295 (NoFixNeeded): Vtop__ALLcls.cpp and other combined files negates parallel compilatio...
This is already optional. Just set VM_PARALLEL_BUILDS=1 when you call make.
Wilson Snyder
08:00 PM Issue #1295 (NoFixNeeded): Vtop__ALLcls.cpp and other combined files negates parallel compilatio...
I have been working on trying to get builds of simulations using Verilator to be higher performance, both in the buil... Rob Stoddard

03/28/2018

10:59 PM Issue #1294 (Confirmed): Connecting the wrong interface to a port does not cause an error
Seems an OK spot, I'd still compare the pointers as you do to speed things up, but then add an "&& " check on the nam... Wilson Snyder
03:35 PM Issue #1294 (Closed): Connecting the wrong interface to a port does not cause an error
Please see the GitHub branch for a test and a not-quite-there-yet fix:
https://github.com/toddstrader/verilator-dev/...
Todd Strader

03/17/2018

04:03 PM Issue #1284 (Closed): Unsupported --annotate-min command line argument for verilator_coverage tool
In 3.922.
Wilson Snyder
04:03 PM Issue #1274 (Closed): Pullup / Pulldown on arrays causes internal crash
In 3.922.
Wilson Snyder
04:03 PM Issue #1285 (Closed): scr1 test suite: built-in system functions only work when the return value ...
In 3.922.
Wilson Snyder
04:03 PM Issue #1281 (Closed): Trig functions
In 3.922.
Wilson Snyder

03/13/2018

03:23 AM Issue #1292: scr1 test suite: |-> and |=> operators are unsupported in assertions
I'd certainly like to help. I'm on a specific mission right now, so it might take a while for me to get around to it,... Joel Holdsworth
01:33 AM Issue #1292 (Confirmed): scr1 test suite: |-> and |=> operators are unsupported in assertions
Joel, perhaps you'd like to try a fix? First make a test case (see internals.txt), then parse it, then finally upgra... Wilson Snyder
01:19 AM Issue #1292: scr1 test suite: |-> and |=> operators are unsupported in assertions
70% of the asserts in scr1 use "|->", so just having that one implemented would cut down the ifdefs (and increase the... Joel Holdsworth
12:51 AM Issue #1292: scr1 test suite: |-> and |=> operators are unsupported in assertions
Verilator does not support the "|->" or "|=>" operators or the sequence expression ("##") operator.
In general, Ve...
John Coiner

03/12/2018

11:45 PM Issue #785: Support for SystemVerilog assertions
Fixed in git towards 3.922 John Coiner
11:44 PM Issue #1290: scr1 test suite: assert properties don't work
Fixed in git towards 3.922 John Coiner

03/11/2018

09:17 PM Issue #1292 (Feature): scr1 test suite: |-> and |=> operators are unsupported in assertions
Code like this fails to build:... Joel Holdsworth
02:56 PM Issue #1290 (Closed): scr1 test suite: assert properties don't work
John Coiner
02:55 PM Issue #1290: scr1 test suite: assert properties don't work
Here's the fix.
commit c8cf2afb15860722e19c4ea6dd7ca0bc74010fac (HEAD -> master, origin/master, origin/HEAD)
Au...
John Coiner
02:56 PM Issue #785 (Closed): Support for SystemVerilog assertions
John Coiner
02:56 PM Issue #785: Support for SystemVerilog assertions
Here's the fix.
commit c8cf2afb15860722e19c4ea6dd7ca0bc74010fac (HEAD -> master, origin/master, origin/HEAD)
Au...
John Coiner

03/10/2018

10:50 PM Issue #1290 (Confirmed): scr1 test suite: assert properties don't work
John, thanks for looking.
Wilson Snyder
06:29 PM Issue #1290: scr1 test suite: assert properties don't work
Thanks. I discovered that concurrent asserts are always clocked in verilog.
So this is a dup of 785.
John Coiner
06:22 PM Issue #1290: scr1 test suite: assert properties don't work
You're right - the scr1 tests are all clocked. My example was a bit too simplified!
Great news that you're working...
Joel Holdsworth
06:13 PM Issue #1290: scr1 test suite: assert properties don't work
For that matter, does verilog even permit unclocked 'assert property' statements? I'm no language lawyer, and I don't... John Coiner
05:55 PM Issue #1290: scr1 test suite: assert properties don't work
Hi Joel,
I'm working on issue 785 which could be considered a dup:
https://www.veripool.org/issues/785-Verilato...
John Coiner
04:18 AM Issue #1290 (Closed): scr1 test suite: assert properties don't work
The following SystemVerilog code fails to build...... Joel Holdsworth
08:32 PM Issue #1288: scr1 test suite: In some cases mixed assignment to struct member fails
Perfect- thansk! Joel Holdsworth
07:17 PM Issue #1288: scr1 test suite: In some cases mixed assignment to struct member fails
Good point, similar suggested comments added to git.
Wilson Snyder
07:00 PM Issue #1288: scr1 test suite: In some cases mixed assignment to struct member fails
Ok -- now I feel silly.
My feedback is that - expected that -Wno-XX would only affect warnings, not errors. Would ...
Joel Holdsworth
05:51 PM Issue #1288: scr1 test suite: In some cases mixed assignment to struct member fails
Use -Wno-BLKANDNBLK
Wilson Snyder
01:43 AM Issue #1288: scr1 test suite: In some cases mixed assignment to struct member fails
Am I being obtuse? I can't see a way to disable the error at run-time. Joel Holdsworth
06:33 PM Issue #785: Support for SystemVerilog assertions
UPDATE: there IS a fundamental difficulty supporting unclocked combinational concurrent asserts -- they're not allowe... John Coiner
05:50 PM Issue #1291 (WillNotFix): scr1 test suite: delayed always blocks are unsupported
Correct, clocks must come from the C side. At least until events are supported which is long off.
Note you can tur...
Wilson Snyder
04:16 PM Issue #1291: scr1 test suite: delayed always blocks are unsupported
RTFM.... I see this isn't going to work Joel Holdsworth
05:17 AM Issue #1291 (WillNotFix): scr1 test suite: delayed always blocks are unsupported
This code generates a warning:... Joel Holdsworth
04:21 AM Issue #1286: scr1 test suite: processing passes get stuck, and allocate huge amounts of system RA...
The block was 16Mb in size. Fortunately nothing in the test suite needs this much memory, so I reduced it to 64kB, an... Joel Holdsworth

03/09/2018

09:46 PM Issue #785: Support for SystemVerilog assertions
I'll have a fix for this shortly.
Still NOT supported will be:
* "|->" syntax
* "##" syntax
* referenc...
John Coiner
08:05 PM Issue #1287 (WillNotFix): scr1 test suite: SystemVerilog nested @ blocks are not supported
Turn it into a FSM, e.g.... Wilson Snyder
05:06 PM Issue #1287: scr1 test suite: SystemVerilog nested @ blocks are not supported
Makes sense.
So here is the relevant code: https://github.com/syntacore/scr1/blob/master/src/tb/scr1_top_tb_ahb.sv...
Joel Holdsworth
04:50 AM Issue #1287 (AskedReporter): scr1 test suite: SystemVerilog nested @ blocks are not supported
Keeping open in case I'm misunderstanding what is needed...
Verilator is not an event based simulator and requires...
Wilson Snyder
05:20 PM Issue #1285: scr1 test suite: built-in system functions only work when the return value is assigned
Nice! Thanks for fixing it so quickly Joel Holdsworth
04:42 AM Issue #1285 (Resolved): scr1 test suite: built-in system functions only work when the return valu...
Simple enough, mapped all system tasks to be allowed as functions. Thanks for the report.
Fixed in git towards 3.9...
Wilson Snyder
05:10 PM Issue #1286: scr1 test suite: processing passes get stuck, and allocate huge amounts of system RA...
It would be nice to get an error or a warning. I only figured out the source of the problem by reading the file & lin... Joel Holdsworth
04:45 AM Issue #1286 (Confirmed): scr1 test suite: processing passes get stuck, and allocate huge amounts ...
Verilator needs enough memory to fit the entire model, times some inefficiency factor.
The fix could be to throw a...
Wilson Snyder
05:02 PM Issue #1289: scr1 test suite: string.hextoa is not implemented
Sure, I don't mind having a look. Joel Holdsworth
04:57 AM Issue #1289 (Confirmed): scr1 test suite: string.hextoa is not implemented
Wilson Snyder
04:57 AM Issue #1289: scr1 test suite: string.hextoa is not implemented
Perhaps you would like to attempt a patch? First make a test case (see internals.txt) which passes on another simula... Wilson Snyder
05:07 AM Issue #1288 (Confirmed): scr1 test suite: In some cases mixed assignment to struct member fails
Added this to the documentation of this error:
"It is generally safe to disable this error when one of the assig...
Wilson Snyder
04:58 AM Issue #1276 (AskedReporter): vcd trace splits packed data type when it comes through a typedef
Still awaiting a test case... Thanks
Wilson Snyder

03/08/2018

11:43 PM Issue #1289 (Closed): scr1 test suite: string.hextoa is not implemented
The follow code SystemVerilog code fails to build...... Joel Holdsworth
11:35 PM Issue #1288 (Confirmed): scr1 test suite: In some cases mixed assignment to struct member fails
This SystemVerilog code...... Joel Holdsworth
11:32 PM Issue #1287 (WillNotFix): scr1 test suite: SystemVerilog nested @ blocks are not supported
The follow SystemVerilog code fails to parse...... Joel Holdsworth
11:30 PM Issue #1286 (Confirmed): scr1 test suite: processing passes get stuck, and allocate huge amounts ...
Verilator gets stuck allocating huge amounts of memory when processing SystemVerilog code like this...... Joel Holdsworth
11:26 PM Issue #1285 (Closed): scr1 test suite: built-in system functions only work when the return value ...
Building this test code fails...... Joel Holdsworth
12:54 AM Issue #1284 (Resolved): Unsupported --annotate-min command line argument for verilator_coverage tool
Thanks for the great patch. Pushed to git towards 3.922.
Wilson Snyder

03/07/2018

11:16 PM Issue #1284 (Closed): Unsupported --annotate-min command line argument for verilator_coverage tool
Hi,
*--annotate-min* command line argument for *verilator_coverage* tool is not supported. Missing implementation ...
Tymoteusz Blazejczyk
 

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