Activity
From 03/18/2018 to 04/16/2018
04/15/2018
- 11:33 AM Issue #1300 (NoFixNeeded): include file verilated.h not being able to recognize from path.
- I'm compiling a SystemVerilog module, after I run "verilator --cc bsg_hypotenuse.v --exe" and then "make -j -f Vbsg_h...
04/05/2018
- 01:04 AM Issue #1294 (Resolved): Connecting the wrong interface to a port does not cause an error
- Good stuff! Thanks.
Merged into git towards 3.924.
04/02/2018
- 06:21 PM Issue #1294: Connecting the wrong interface to a port does not cause an error
- I think the latest commit takes care of everything:
https://github.com/toddstrader/verilator-dev/tree/wrong_intf
04/01/2018
- 11:52 AM Issue #1297 (Duplicate): 1 Bit signed values
- This was reported by another user last week, and is already fixed in the git version (but not released yet).
Thank... - 05:46 AM Issue #1297 (Duplicate): 1 Bit signed values
- For example having the port: "input signed a" will lead to the following error:
syntax error, unexpected IDENTIFIE...
03/30/2018
- 06:32 AM Issue #1296: SystemVerilog logic array inside struct should warn on bad index
- Wilson Snyder wrote:
> No.
>
> logic [31:20] imm;
> $display("instr.imm[11]: %d <-- should be 1 ... - 12:35 AM Issue #1296 (Feature): SystemVerilog logic array inside struct should warn on bad index
- No.
logic [31:20] imm;
$display("instr.imm[11]: %d <-- should be 1 !!", instr.imm[11]);
Imm is...
03/29/2018
- 11:27 PM Issue #1296 (NoFixNeeded): SystemVerilog logic array inside struct should warn on bad index
- It looks like when you have a logic array inside a struct, and you try to access a bit of that field directly, they i...
- 08:52 PM Issue #1295 (NoFixNeeded): Vtop__ALLcls.cpp and other combined files negates parallel compilatio...
- This is already optional. Just set VM_PARALLEL_BUILDS=1 when you call make.
- 08:00 PM Issue #1295 (NoFixNeeded): Vtop__ALLcls.cpp and other combined files negates parallel compilatio...
- I have been working on trying to get builds of simulations using Verilator to be higher performance, both in the buil...
03/28/2018
- 10:59 PM Issue #1294 (Confirmed): Connecting the wrong interface to a port does not cause an error
- Seems an OK spot, I'd still compare the pointers as you do to speed things up, but then add an "&& " check on the nam...
- 03:35 PM Issue #1294 (Closed): Connecting the wrong interface to a port does not cause an error
- Please see the GitHub branch for a test and a not-quite-there-yet fix:
https://github.com/toddstrader/verilator-dev/...
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