Verilator

04/21/2018

11:40 AM Issue #1305 (Confirmed): Error messages do not contain hierarchical information

I can see how that is useful.
In theory try from the nodep causing the error to follow backp() looking for any Ast... Wilson Snyder

04/20/2018

03:37 PM Issue #1305 (Resolved): Error messages do not contain hierarchical information

Please see the t_func_const2_bad test in:
https://github.com/toddstrader/verilator-dev/tree/mod_stack_trace
I cur... Todd Strader

04/19/2018

07:05 PM Issue #1303: VCD Filter Files

Linking to my "hotfix" that implements the filter files as described above: https://github.com/wallento/verilator/com... Stefan Wallentowitz

07:02 PM Issue #1303: VCD Filter Files

Thanks, I assume you mean this vpi stuff under contrib. By the way I think I meant FST, just double checking with you... Stefan Wallentowitz

02:15 PM Issue #1303: VCD Filter Files

Great. BTW I would suggest a hand written writer rather than the gtkwave-sources one for generic simulators, as VPI i... Wilson Snyder

02:08 PM Issue #1303: VCD Filter Files

Hi Wilson,
thanks a lot. I will have a look at LXT2 trace writers too. My first implementation prototype works wel... Stefan Wallentowitz

02:01 PM Issue #1303 (Assigned): VCD Filter Files

I'm open to such a patch, however it maybe more useful to write a new trace writer that uses the gtkwave format.
A... Wilson Snyder

06:35 PM Issue #1301: Whitespaces in codebase

Hi Wilson,
thanks a lot for pointing out. I obviously missed that this is the GNU coding style. Fully agree to you... Stefan Wallentowitz

01:53 PM Issue #1301 (WillNotFix): Whitespaces in codebase

Verilator used the gnu standard indentation of 4, with tabs always 8.
However I have given up on this as the world... Wilson Snyder

02:09 PM Issue #1302 (Assigned): Doxygen documentation

Doxygen fixups are welcome, however note the develop-v4 branch should be used for major updates.
Please however ke... Wilson Snyder

02:01 PM Issue #1304: Codebase: Macro to iterate over nodes of known type

Thanks for pointing this out, I was not aware of this branch so far. Stefan Wallentowitz

01:57 PM Issue #1304: Codebase: Macro to iterate over nodes of known type

I need to think if I like this.
However please use the develop-v4 branch which will become 4.000 for any large-tou... Wilson Snyder

04/18/2018

02:48 PM Issue #1304: Codebase: Macro to iterate over nodes of known type

Sorry, I copied the commit text and now found how strange it looks here. Stefan Wallentowitz

02:29 PM Issue #1304 (WillNotFix): Codebase: Macro to iterate over nodes of known type

There is a pattern in the codebase when a list of nodes is iterated and the type of each of the nodes is equal and kn... Stefan Wallentowitz

08:11 AM Issue #1303 (NoFixNeeded): VCD Filter Files

Hi,
what recently bothered me a lot was debugging my own state machines. Some of those grew incredibly large (~90 ... Stefan Wallentowitz

08:04 AM Issue #1302 (NoFixNeeded): Doxygen documentation

Hi Wilson,
I have started looking in some things to do in Verilator and I am still on the learning curve for the c... Stefan Wallentowitz

07:58 AM Issue #1301 (WillNotFix): Whitespaces in codebase

Hi Wilson,
without the intent to start a religious war ;)
I am wondering if you have any strong feelings about wh... Stefan Wallentowitz

04/17/2018

02:50 PM Issue #1292: scr1 test suite: |-> and |=> operators are unsupported in assertions

Hi Stefan, I didn't look at the issue yet. Go ahead if you want to add support.
Joel Joel Holdsworth

11:20 AM Issue #1292: scr1 test suite: |-> and |=> operators are unsupported in assertions

Hi,
I would be happy to contribute on that one. Joel, did you start already? If so, can you please contact me (ste... Stefan Wallentowitz

11:26 AM Issue #1300: include file verilated.h not being able to recognize from path.

Dear Kunal,
I am confused about your description. Can you please clarify how you build it and what you do when you... Stefan Wallentowitz

04/15/2018

11:33 AM Issue #1300 (NoFixNeeded): include file verilated.h not being able to recognize from path.

I'm compiling a SystemVerilog module, after I run "verilator --cc bsg_hypotenuse.v --exe" and then "make -j -f Vbsg_h... Kunal Gulati

04/05/2018

01:04 AM Issue #1294 (Resolved): Connecting the wrong interface to a port does not cause an error

Good stuff! Thanks.
Merged into git towards 3.924.
Wilson Snyder

04/02/2018

06:21 PM Issue #1294: Connecting the wrong interface to a port does not cause an error

I think the latest commit takes care of everything:
https://github.com/toddstrader/verilator-dev/tree/wrong_intf Todd Strader

04/01/2018

11:52 AM Issue #1297 (Duplicate): 1 Bit signed values

This was reported by another user last week, and is already fixed in the git version (but not released yet).
Thank... Wilson Snyder

05:46 AM Issue #1297 (Duplicate): 1 Bit signed values

For example having the port: "input signed a" will lead to the following error:
syntax error, unexpected IDENTIFIE... Kevin Townsend

03/30/2018

06:32 AM Issue #1296: SystemVerilog logic array inside struct should warn on bad index

Wilson Snyder wrote:
> No.
>
> logic [31:20] imm;
> $display("instr.imm[11]: %d <-- should be 1 ... Sergi Granell

12:35 AM Issue #1296 (Feature): SystemVerilog logic array inside struct should warn on bad index

No.
logic [31:20] imm;
$display("instr.imm[11]: %d <-- should be 1 !!", instr.imm[11]);
Imm is... Wilson Snyder

03/29/2018

11:27 PM Issue #1296 (NoFixNeeded): SystemVerilog logic array inside struct should warn on bad index

It looks like when you have a logic array inside a struct, and you try to access a bit of that field directly, they i... Sergi Granell

08:52 PM Issue #1295 (NoFixNeeded): Vtop__ALLcls.cpp and other combined files negates parallel compilatio...

This is already optional. Just set VM_PARALLEL_BUILDS=1 when you call make.
Wilson Snyder

08:00 PM Issue #1295 (NoFixNeeded): Vtop__ALLcls.cpp and other combined files negates parallel compilatio...

I have been working on trying to get builds of simulations using Verilator to be higher performance, both in the buil... Rob Stoddard

03/28/2018

10:59 PM Issue #1294 (Confirmed): Connecting the wrong interface to a port does not cause an error

Seems an OK spot, I'd still compare the pointers as you do to speed things up, but then add an "&& " check on the nam... Wilson Snyder

03:35 PM Issue #1294 (Closed): Connecting the wrong interface to a port does not cause an error

Please see the GitHub branch for a test and a not-quite-there-yet fix:
https://github.com/toddstrader/verilator-dev/... Todd Strader