Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Activity

From 05/02/2018 to 05/31/2018

05/26/2018

12:05 PM Usage: RE: Verilator generated picorv32 coredump
The error means that the testbench called $stop, which probably means something's wrong in the simulation expectation... Wilson Snyder

05/24/2018

11:25 PM Usage: Verilator generated picorv32 coredump
This is the command used:... Dragon Ware

05/06/2018

02:16 PM Development: RE: Using Verilator with Buck
It's not clear how what you propose would work when a user changes say design "A" to need a new include or have a new... Wilson Snyder

05/05/2018

04:20 PM Development: RE: Using Verilator with Buck
Wilson, thank you for taking the time to answer. I think some clarification on my end is required and let me make mor... Arjen Roodselaar
12:05 PM Development: RE: Using Verilator with Buck
I think you may be under the misimpression that each module directly corresponds to a "separable" C++ file after Veri... Wilson Snyder
06:59 AM Development: Using Verilator with Buck
I have been working on a project that has both a sizable amount of C++ as well as SystemVerilog. I use Verilator to w... Arjen Roodselaar
 

Also available in: Atom