Project

General

Profile

[logo] 
 
Home
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Activity

From 05/25/2018 to 06/23/2018

06/08/2018

12:16 AM Development: RE: Verilator doesn't support UTF-8 formated verilog files.
I just want to use multi-language with verilator.
Because I can use a little c codes with this. And gcc does. And I ...
HyungKi Jeong

06/07/2018

12:36 PM Development: RE: Verilator doesn't support UTF-8 formated verilog files.
What is another simulator that supports it? It seems neither VCS nor NC-Verilog do, and I'm reluctant to add somethi... Wilson Snyder

06/05/2018

06:11 AM Development: Verilator doesn't support UTF-8 formated verilog files.
verilator doesn't support UTF-8 format.<br>
It makes error as shown below.
%Error: Specified --top-module 'top' w...
HyungKi Jeong
02:20 AM Usage: RE: non-constant ARRAYSEL error
I add a issues 1315. Thanks
Marshal qiao
02:05 AM Usage: RE: error: missed initializing elements
I update the newest version, then this demo pass. thanks Marshal qiao

06/01/2018

10:49 AM Usage: RE: error: missed initializing elements
This works fine for me, are you sure you're using the most recent version?
Wilson Snyder
08:20 AM Usage: error: missed initializing elements
hello, i want to test some syntax in my code , and meet some error。
my test code:
module ex28
(
i...
Marshal qiao
10:40 AM Usage: RE: non-constant ARRAYSEL error
Using an array in a function called from a parameter is not currently supported.
If you'd like to file a feature b...
Wilson Snyder
02:53 AM Usage: non-constant ARRAYSEL error
attach file sv_code.png is my code.
Running verilator on the code gives some errors.
Marshal qiao

05/26/2018

12:05 PM Usage: RE: Verilator generated picorv32 coredump
The error means that the testbench called $stop, which probably means something's wrong in the simulation expectation... Wilson Snyder
 

Also available in: Atom