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Activity

From 07/15/2018 to 08/13/2018

08/12/2018

10:24 AM Issue #1328 (Confirmed): Parameter with type string cause compile error when passed to $readmemh(...
I suspect it is legal to use a string instead of Verilog bitvector-as-string.
Could you attempt a patch, and also...
Wilson Snyder

08/11/2018

09:31 PM Issue #1328 (NoFixNeeded): Parameter with type string cause compile error when passed to $readmem...
With my limited understanding of the SV type system I expect the following to work:... Arjen Roodselaar
03:42 PM Issue #1326 (AskedReporter): Comb Logic order problem
Verilator internally should treat assigns identically to always_comb, so probably something more complicated is going... Wilson Snyder
03:37 PM Issue #1327: Strange initialisation behaviour with "VinpClk" cloned clock variables
I suspect the code should be changed to at init time after rand reset, set all last vars = the normal non-last value.... Wilson Snyder

08/09/2018

01:32 PM Issue #1327 (Closed): Strange initialisation behaviour with "VinpClk" cloned clock variables
We're seeing a strange behaviour in our system testbench. I've tracked
it down to a problem with (seemingly) spuriou...
Rupert Swarbrick

08/06/2018

05:25 AM Issue #1326: Comb Logic order problem
... Kyunghwan Cho
05:18 AM Issue #1326 (NotEnoughInfo): Comb Logic order problem

When trying to compile systemverilog source, I found the following issues.
alu0_opd_update reflects the previous...
Kyunghwan Cho
 

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