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Activity

From 07/23/2018 to 08/21/2018

08/21/2018

10:28 PM Issue #1328 (AskedReporter): Parameter with type string cause compile error when passed to $readm...
Are you sure you're using the latest version, I can't recreate this and suspect it may have been fixed in 3.922.
Wilson Snyder
10:09 PM Issue #1330 (Resolved): Broken link error when inlining functions under while loops
Thanks for the good test case, this was related to certain function calls under while loops.
Fixed in git towards ...
Wilson Snyder

08/19/2018

06:31 AM Issue #1329 (AskedReporter): Compile error "expected unqualified-id before numeric constant"
Sorry you are having problems.
What OS version?
What flex version?
What is the code around the lines the com...
Wilson Snyder

08/16/2018

10:17 AM Issue #1330 (Closed): Broken link error when inlining functions under while loops
This internal error occurs when verilating the attached test case, but only when the --trace switch is specified
v...
Julien Margetts

08/14/2018

08:12 PM Issue #1329 (NoFixNeeded): Compile error "expected unqualified-id before numeric constant"
./configure runs without issue, but make fails with the below message. I have tried newer versions of flex/bison, bu... Shawn Boshart

08/12/2018

10:24 AM Issue #1328 (Confirmed): Parameter with type string cause compile error when passed to $readmemh(...
I suspect it is legal to use a string instead of Verilog bitvector-as-string.
Could you attempt a patch, and also...
Wilson Snyder

08/11/2018

09:31 PM Issue #1328 (NoFixNeeded): Parameter with type string cause compile error when passed to $readmem...
With my limited understanding of the SV type system I expect the following to work:... Arjen Roodselaar
03:42 PM Issue #1326 (AskedReporter): Comb Logic order problem
Verilator internally should treat assigns identically to always_comb, so probably something more complicated is going... Wilson Snyder
03:37 PM Issue #1327: Strange initialisation behaviour with "VinpClk" cloned clock variables
I suspect the code should be changed to at init time after rand reset, set all last vars = the normal non-last value.... Wilson Snyder

08/09/2018

01:32 PM Issue #1327 (Closed): Strange initialisation behaviour with "VinpClk" cloned clock variables
We're seeing a strange behaviour in our system testbench. I've tracked
it down to a problem with (seemingly) spuriou...
Rupert Swarbrick

08/06/2018

05:25 AM Issue #1326: Comb Logic order problem
... Kyunghwan Cho
05:18 AM Issue #1326 (NotEnoughInfo): Comb Logic order problem

When trying to compile systemverilog source, I found the following issues.
alu0_opd_update reflects the previous...
Kyunghwan Cho
 

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