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Activity

From 10/20/2018 to 11/18/2018

11/18/2018

10:26 AM Development: RE: Requiring C++11 compiler
this turns out to be resolved by closing msys2 and reopening it. Maybe I was following some bad instructions from Spi... Thomas Dye
10:11 AM Development: RE: Requiring C++11 compiler
apparently using msys2, g++ doesn't have a C++11 compatible compiler. Thomas Dye

11/17/2018

11:23 AM Usage: RE: threaded compile error message
That's small, about 5K instructions in the main loop. This suggests you might be getting around 1M cycles/second (mi... Wilson Snyder

11/16/2018

04:22 PM Usage: RE: threaded compile error message
I haven't looked at a lot of the resulting stats files, so I don't know if this counts as large or small. ... David Stanford

11/15/2018

11:47 PM Usage: RE: threaded compile error message
It isn't associated with an exact file so the inline pragma won't work. However we have several self tests that check... Wilson Snyder
09:56 PM Usage: RE: threaded compile error message
I'm having problems disabling this warning. I've tried lint_off / lint_on as recommended in the warning message aroun... David Stanford
09:36 PM Usage: RE: threaded compile error message
What's the instruction count total last column? Guessing this is a fairly small design? Small designs are unlikely ... Wilson Snyder
09:08 PM Usage: RE: threaded compile error message
Well, yep looks like the parallelism factor is pretty low on this design. ... David Stanford

11/14/2018

11:56 PM Usage: RE: threaded compile error message
Roughly yes. It tries to look for many parallel tasks (many per thread). It can't find enough, but you may still if ... Wilson Snyder
06:02 PM Usage: threaded compile error message
I'm getting the following error message when trying to do a multi-threaded compile: ... David Stanford

11/01/2018

11:53 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Well done, pushed to git towards 4.008.
Wilson Snyder
04:50 AM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
I have attached the patch for the hier changes to --xml-only option. The V3EmitXml.cpp has been updated to output the... Kanad Kanhere

10/31/2018

12:37 AM Usage: RE: bug in fst_config.h
Fine :) HyungKi Jeong

10/30/2018

10:18 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Great! I called it origName to match the caps of destName.
Pushed to git towards 4.008.
Wilson Snyder
09:18 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
I have attached the git patch for the origname change. Apologies if this is not the right way to provide the patch. I... Kanad Kanhere
11:42 AM Usage: RE: bug in fst_config.h
Sorry botched that first time, fixed in git towards 4.008.
Wilson Snyder
10:36 AM Usage: RE: bug in fst_config.h
on v4.006 HyungKi Jeong
10:32 AM Usage: bug in fst_config.h
"if endif" is need for MINGW.<br>
but already 'HAVE_ALLOCA_H' is defined previous line.<br>
*-#define HAVE_ALLOCA_H...
HyungKi Jeong
10:46 AM Usage: make program fault with MinGW on v4.006
In MinGW64 + MSYS(windows) system.<br>
Program fault is occurred at "verilated_fst_c.cpp" at line #74, on v4.006<br>...
HyungKi Jeong

10/28/2018

07:25 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Modules can be identified with just a "grep '<module'" so doesn't seem worth duplicating them.
In contrast the cel...
Wilson Snyder
05:32 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
I can definitely provide the patch to output origname.
Infact, if it is fine with you, I think the output xml should...
Kanad Kanhere
12:16 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Ah --xml-only should have been documented, it started off experimental then forgot to upgrade it. Fixed in git.
A...
Wilson Snyder
03:09 AM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
I just went through the source again to check about the xml format you mentioned and came across the undocumented --x... Kanad Kanhere
02:35 AM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
The biggest difference with Vhier is that the output will contain trimmed list of modules and interfaces, i.e. those ... Kanad Kanhere

10/27/2018

06:43 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
I'd suggest the switch be --xml-hier.
How is your trimmed_module_files different from normal vhier's module_files?...
Wilson Snyder
05:30 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Hi, Thanks for the reply.
So the below is what I plan to do. Kindly let me know if you have any comments or concerns...
Kanad Kanhere

10/26/2018

10:20 PM Development: RE: std::abort and others in error handlers
Define VL_USER_FINISH and VL_USER_FATAL, then provide your own vl_finish/vl_fatal functions and you should be all set.
Wilson Snyder
10:04 PM Development: std::abort and others in error handlers
Hello,
is it possible to replace std::abort, std::exit calls in handlers of errors with proper exception?
(I can ...
Michal Orsak
01:18 AM Development: RE: can verilator -E preserve comments?
Not until now. Added --pp-comments to git, towards 4.006.
Wilson Snyder

10/25/2018

08:33 PM Development: can verilator -E preserve comments?
gcc supports the -C flag to cause the preprocessor to preserve comments.
Is there a similar mechanism for verilato...
Robert Henry
06:57 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Your approach makes sense. Unless it doesn't work for some reason (why), could you please make your visitor output i... Wilson Snyder
04:03 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Hi Wilson,
I am Hayden's colleague and would want to elaborate on a few things.
The syntax that doesn't work for...
Kanad Kanhere

10/23/2018

09:49 PM Usage: RE: Getting a list of module and SystemVerilog interface dependencies
I assume when you say you tried vhier, you don't mean there's a literal syntax problem as it should be able to handle... Wilson Snyder
05:18 PM Usage: Getting a list of module and SystemVerilog interface dependencies
My team and I have been working on getting a list of the module and interface dependencies of a given Verilated modul... Hayden Roche
 

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