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Activity

From 10/28/2018 to 11/26/2018

11/26/2018

10:30 PM RISC-V Contest Chooses Verilator
The 2018 RISC-V design contest has announced all submissions must be submitted only using Verilator.
The contest i...
Wilson Snyder

11/25/2018

11:47 PM Issue #1349 (Assigned): Cygwin verilator_coverage fails due to cygwin bug in getline()
Thanks for figuring out a work around, will need to decide how to best support this. Note the code as written is lega... Wilson Snyder

11/24/2018

08:36 AM Issue #1349: Cygwin verilator_coverage fails due to cygwin bug in getline()
Hi,
I had exactly this same situation. After some tracing works, I come to this quick and dirty fix:...
Affe Mao

11/23/2018

10:38 AM Issue #1366 (AskedReporter): Large increase in design header file with threads and tracing
When using both threads and tracing (VM_TRACE=1), and separate build steps for the design library (Vdesign__ALL.a) an... Al Grant

11/07/2018

06:42 PM Issue #1365 (Duplicate): False BLKANDNBLK error for different signals in a vector
Please see bug364.
I understand this is annoying, but is a fairly high effort limitation to resolve so hasn't been...
Wilson Snyder

11/06/2018

11:14 AM Issue #1365 (Duplicate): False BLKANDNBLK error for different signals in a vector
... Al Grant

11/01/2018

11:04 PM Issue #1364 (Resolved): Verilator hangs in malloc() when assignment pattern key is not found
Thanks for the report. Fixed in git towards 4.008.
Wilson Snyder
06:38 PM Issue #1364: Verilator hangs in malloc() when assignment pattern key is not found
Confirmed this happens in 4.006 as well Matt Myers
05:08 PM Issue #1364 (Closed): Verilator hangs in malloc() when assignment pattern key is not found
The following code correctly gives an error message:
%Error: Assignment pattern key 'valids' not found as member
...
Matt Myers

10/31/2018

12:56 AM Issue #1360 (Resolved): Adding support for passing by reference
Fixed in git towards 4.008.
I added only a few simple tests, I expect some problems as you try to use refs. Pleas...
Wilson Snyder
 

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