Activity
From 11/07/2018 to 12/06/2018
12/06/2018
- 05:10 PM Issue #1373: Cannot write to top-level tristate ports
- > Would you be willing to take a look at fixing this?
Hm I am not currently set up to compile verilator from sourc... - 01:38 AM Issue #1373 (Feature): Cannot write to top-level tristate ports
- Verilator doesn't currently support tristate resolution that is a mix of external and internal drivers.
What it sh... - 12:28 PM Issue #1372: XML output insufficiently qualified
- Huh, I'll see what's up with git.
Meantime attached.
- 12:24 PM Issue #1372: XML output insufficiently qualified
- http://git.veripool.org/git/verilator seems to be down, so I can't see your final version.
- 12:14 PM Issue #1372 (Resolved): XML output insufficiently qualified
- Great, fixed in git towards 4.010.
Note used empty() instead of length() as Google static lint tool will complain ... - 11:50 AM Issue #1372: XML output insufficiently qualified
- That version failed in a rather obvious way, please find attached third, and hopefully final attempt.
- 09:45 AM Issue #1372: XML output insufficiently qualified
- This is a second attempt, which tries harder to dump the more interesting information, and also identifies interfaces...
- 01:07 AM Issue #1372 (AskedReporter): XML output insufficiently qualified
- I'm fine with this concept but can you instead please update the patch to add a method to VDirection and AstVarType c...
12/05/2018
- 06:30 PM Issue #1373 (Feature): Cannot write to top-level tristate ports
- DESCRIPTION of the bug:
Top level has bidirectional port bus1 and direction bit en1. When
en1==0, bus1 is used as ... - 04:19 PM Issue #1372 (Closed): XML output insufficiently qualified
- The xml output generated by the verilator --xmlonly command is insufficiently qualified when it comes to toplevel por...
12/04/2018
- 06:46 AM Issue #1369: Raise error / warning on continous assignment to reg
- Thank you for the fix! verilator now raises error on _internal_reg_ but does not recognize the case of _out_ signal i...
12/01/2018
- 08:17 PM Issue #1370 (Closed): Slow file compiled with OPT_FAST when --output-split is used
- In 4.008.
- 08:17 PM Issue #1349 (Closed): Cygwin verilator_coverage fails due to cygwin bug in getline()
- In 4.008.
- 08:17 PM Issue #1364 (Closed): Verilator hangs in malloc() when assignment pattern key is not found
- In 4.008.
- 08:17 PM Issue #1369 (Closed): Raise error / warning on continous assignment to reg
- In 4.008.
- 03:25 PM Issue #1369 (Resolved): Raise error / warning on continous assignment to reg
- Fixed in git towards 4.008.
- 08:17 PM Issue #1360 (Closed): Adding support for passing by reference
- In 4.008.
11/30/2018
- 10:26 AM Issue #1370 (Resolved): Slow file compiled with OPT_FAST when --output-split is used
- Good catch, the tests weren't checking the right options were used and of course what isn't tested is broken ;)
Fi... - 06:50 AM Issue #1369: Raise error / warning on continous assignment to reg
- Xilinx ISE 14.7 syntheser complains about this:...
11/29/2018
- 11:13 PM Issue #1366 (AskedReporter): Large increase in design header file with threads and tracing
- Can you share an example of the sort of things that are getting massively expanded (e.g. are in the combined file but...
- 11:12 PM Issue #1369 (Feature): Raise error / warning on continous assignment to reg
- I believe the code sent is legal in SystemVerilog, so no warning is appropriate. What complains and does it support ...
- 01:09 PM Issue #1370 (Closed): Slow file compiled with OPT_FAST when --output-split is used
- Hi, I'm trying to speed up the build time of a moderately large verilator model.
So I'm verilating with --output-...
11/28/2018
- 01:52 PM Issue #1369 (Confirmed): Raise error / warning on continous assignment to reg
- Verilator does not throw error / warning on continuous assignment to a register. See the following example:
conten...
11/27/2018
- 10:05 AM Issue #1367 (NoFixNeeded): [newbie] Is there a way to keep SystemC port types "sc_uint<xx>" ?
- --pins-bv 1 might do what you want. See also --pins-sc-biguint.
- 06:20 AM Issue #1367 (NoFixNeeded): [newbie] Is there a way to keep SystemC port types "sc_uint<xx>" ?
- Understood that, it will suffer in sim speed. It would be good to keep the interface so simulations can be "true". ...
- 12:13 AM Issue #1349 (Resolved): Cygwin verilator_coverage fails due to cygwin bug in getline()
- Thanks for the patch.
Work around added to git towards 4.008.
11/25/2018
- 11:47 PM Issue #1349 (Assigned): Cygwin verilator_coverage fails due to cygwin bug in getline()
- Thanks for figuring out a work around, will need to decide how to best support this. Note the code as written is lega...
11/24/2018
- 08:36 AM Issue #1349: Cygwin verilator_coverage fails due to cygwin bug in getline()
- Hi,
I had exactly this same situation. After some tracing works, I come to this quick and dirty fix:...
11/23/2018
- 10:38 AM Issue #1366 (AskedReporter): Large increase in design header file with threads and tracing
- When using both threads and tracing (VM_TRACE=1), and separate build steps for the design library (Vdesign__ALL.a) an...
11/07/2018
- 06:42 PM Issue #1365 (Duplicate): False BLKANDNBLK error for different signals in a vector
- Please see bug364.
I understand this is annoying, but is a fairly high effort limitation to resolve so hasn't been...
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