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Activity

From 11/20/2018 to 12/19/2018

12/19/2018

01:53 AM Issue #1376 (Resolved): Incorrect array contents in FST and LXT2 output formats
Thanks for the report and pointing out the fix.
Fixed in git towards 4.010.
Wilson Snyder
01:42 AM Issue #1378 (Resolved): SystemVerilog array initialization crashes verilator with no useful error...
Thanks for the good report.
Simple fix, fixed in git towards 4.010.
Wilson Snyder

12/18/2018

02:05 PM Issue #1378 (Closed): SystemVerilog array initialization crashes verilator with no useful error m...
If we have a SV packed structure with several elements and we try to initialize it as an array list, but the array li... Viktor Tomov

12/16/2018

12:26 AM Issue #1377: Segmentation Fault when tracing is enabled
Perhaps you didn't link with -ggdb?
A test case would be appreciated.
Wilson Snyder

12/15/2018

11:22 PM Issue #1377: Segmentation Fault when tracing is enabled
Wilson Snyder wrote:
> >Program received signal SIGSEGV, Segmentation fault. 0x0000000000026816 in ?? ()
>
> You ...
Aaron Kelly
01:15 PM Issue #1377: Segmentation Fault when tracing is enabled
>Program received signal SIGSEGV, Segmentation fault. 0x0000000000026816 in ?? ()
You need to compile with debug o...
Wilson Snyder
02:36 AM Issue #1377: Segmentation Fault when tracing is enabled
Wilson Snyder wrote:
> Thanks.
>
> There's numerous trace control methods, probably --trace-depth is the first to...
Aaron Kelly
12:43 AM Issue #1377 (AskedReporter): Segmentation Fault when tracing is enabled
Thanks.
There's numerous trace control methods, probably --trace-depth is the first to try, see others in the manu...
Wilson Snyder
12:24 AM Issue #1377 (NotEnoughInfo): Segmentation Fault when tracing is enabled
Hi all,
First off let me thank you for this amazing software - I have compiled a 250k gate design with some of the...
Aaron Kelly

12/13/2018

08:58 PM Issue #1376 (Closed): Incorrect array contents in FST and LXT2 output formats
The bit string created by the VerilatedFst::array2Str() method is incorrect.
The two for() loops should be swapped.
Aleksander Osman
03:19 AM Issue #1372: XML output insufficiently qualified
Applied. No worries, easy as long as you give patches!
Wilson Snyder

12/12/2018

05:11 PM Issue #1372: XML output insufficiently qualified
That resolution didn't last long. It turns out AstVarXRef's are not qualified with the path
of the interface that th...
Jonathan Kimmitt
06:18 AM Issue #1328: Parameter with type string cause compile error when passed to $readmemh(...)
Apologies for the radio silence. Life got in the way of hobby and I wasn't able to look at this. Unfortunately this w... Arjen Roodselaar

12/11/2018

08:43 AM Issue #1372: XML output insufficiently qualified
Thanks. I'm hoping that's enough to get up and running. I am considering this patch provisionally closed.
Jonathan Kimmitt
12:12 AM Issue #1372: XML output insufficiently qualified
Patch 6 pushed.
Wilson Snyder

12/10/2018

05:36 PM Issue #1372: XML output insufficiently qualified
interface modportnames are not mentioned in the typetable (which leaves direction of module interface ports ambiguous... Jonathan Kimmitt
12:26 PM Issue #1372: XML output insufficiently qualified
Patch 5 pushed, no worries!
Wilson Snyder
12:07 PM Issue #1372: XML output insufficiently qualified
Dear Wilson,
I realized too late that the patch previously submitted does not cover dumping port directions for mo...
Jonathan Kimmitt

12/06/2018

05:10 PM Issue #1373: Cannot write to top-level tristate ports
> Would you be willing to take a look at fixing this?
Hm I am not currently set up to compile verilator from sourc...
Stephen Richardson
01:38 AM Issue #1373 (Feature): Cannot write to top-level tristate ports
Verilator doesn't currently support tristate resolution that is a mix of external and internal drivers.
What it sh...
Wilson Snyder
12:28 PM Issue #1372: XML output insufficiently qualified
Huh, I'll see what's up with git.
Meantime attached.
Wilson Snyder
12:24 PM Issue #1372: XML output insufficiently qualified
http://git.veripool.org/git/verilator seems to be down, so I can't see your final version.
Jonathan Kimmitt
12:14 PM Issue #1372 (Resolved): XML output insufficiently qualified
Great, fixed in git towards 4.010.
Note used empty() instead of length() as Google static lint tool will complain ...
Wilson Snyder
11:50 AM Issue #1372: XML output insufficiently qualified
That version failed in a rather obvious way, please find attached third, and hopefully final attempt.
Jonathan Kimmitt
09:45 AM Issue #1372: XML output insufficiently qualified
This is a second attempt, which tries harder to dump the more interesting information, and also identifies interfaces... Jonathan Kimmitt
01:07 AM Issue #1372 (AskedReporter): XML output insufficiently qualified
I'm fine with this concept but can you instead please update the patch to add a method to VDirection and AstVarType c... Wilson Snyder

12/05/2018

06:30 PM Issue #1373 (Feature): Cannot write to top-level tristate ports
DESCRIPTION of the bug:
Top level has bidirectional port bus1 and direction bit en1. When
en1==0, bus1 is used as ...
Stephen Richardson
04:19 PM Issue #1372 (Closed): XML output insufficiently qualified
The xml output generated by the verilator --xmlonly command is insufficiently qualified when it comes to toplevel por... Jonathan Kimmitt

12/04/2018

06:46 AM Issue #1369: Raise error / warning on continous assignment to reg
Thank you for the fix! verilator now raises error on _internal_reg_ but does not recognize the case of _out_ signal i... Peter Gerst

12/01/2018

08:17 PM Issue #1370 (Closed): Slow file compiled with OPT_FAST when --output-split is used
In 4.008.
Wilson Snyder
08:17 PM Issue #1349 (Closed): Cygwin verilator_coverage fails due to cygwin bug in getline()
In 4.008.
Wilson Snyder
08:17 PM Issue #1364 (Closed): Verilator hangs in malloc() when assignment pattern key is not found
In 4.008.
Wilson Snyder
08:17 PM Issue #1369 (Closed): Raise error / warning on continous assignment to reg
In 4.008.
Wilson Snyder
03:25 PM Issue #1369 (Resolved): Raise error / warning on continous assignment to reg
Fixed in git towards 4.008.
Wilson Snyder
08:17 PM Issue #1360 (Closed): Adding support for passing by reference
In 4.008.
Wilson Snyder
08:17 PM Verilator 4.008 Released
* Verilator 4.008 2018-12-01
*** Support "ref" and "const ref" pins and functions, bug1360. [Jake Longo]
*** ...
Wilson Snyder

11/30/2018

10:26 AM Issue #1370 (Resolved): Slow file compiled with OPT_FAST when --output-split is used
Good catch, the tests weren't checking the right options were used and of course what isn't tested is broken ;)
Fi...
Wilson Snyder
06:50 AM Issue #1369: Raise error / warning on continous assignment to reg
Xilinx ISE 14.7 syntheser complains about this:... Peter Gerst

11/29/2018

11:13 PM Issue #1366 (AskedReporter): Large increase in design header file with threads and tracing
Can you share an example of the sort of things that are getting massively expanded (e.g. are in the combined file but... Wilson Snyder
11:12 PM Issue #1369 (Feature): Raise error / warning on continous assignment to reg
I believe the code sent is legal in SystemVerilog, so no warning is appropriate. What complains and does it support ... Wilson Snyder
01:09 PM Issue #1370 (Closed): Slow file compiled with OPT_FAST when --output-split is used
Hi, I'm trying to speed up the build time of a moderately large verilator model.
So I'm verilating with --output-...
Thomas Watts

11/28/2018

01:52 PM Issue #1369 (Closed): Raise error / warning on continous assignment to reg
Verilator does not throw error / warning on continuous assignment to a register. See the following example:
conten...
Peter Gerst

11/27/2018

10:05 AM Issue #1367 (NoFixNeeded): [newbie] Is there a way to keep SystemC port types "sc_uint<xx>" ?
--pins-bv 1 might do what you want. See also --pins-sc-biguint.
Wilson Snyder
06:20 AM Issue #1367 (NoFixNeeded): [newbie] Is there a way to keep SystemC port types "sc_uint<xx>" ?
Understood that, it will suffer in sim speed. It would be good to keep the interface so simulations can be "true". ... Ayewin Oung
12:13 AM Issue #1349 (Resolved): Cygwin verilator_coverage fails due to cygwin bug in getline()
Thanks for the patch.
Work around added to git towards 4.008.
Wilson Snyder

11/26/2018

10:30 PM RISC-V Contest Chooses Verilator
The 2018 RISC-V design contest has announced all submissions must be submitted only using Verilator.
The contest i...
Wilson Snyder

11/25/2018

11:47 PM Issue #1349 (Assigned): Cygwin verilator_coverage fails due to cygwin bug in getline()
Thanks for figuring out a work around, will need to decide how to best support this. Note the code as written is lega... Wilson Snyder

11/24/2018

08:36 AM Issue #1349: Cygwin verilator_coverage fails due to cygwin bug in getline()
Hi,
I had exactly this same situation. After some tracing works, I come to this quick and dirty fix:...
Affe Mao

11/23/2018

10:38 AM Issue #1366 (AskedReporter): Large increase in design header file with threads and tracing
When using both threads and tracing (VM_TRACE=1), and separate build steps for the design library (Vdesign__ALL.a) an... Al Grant
 

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