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Activity

From 12/07/2018 to 01/05/2019

01/05/2019

12:43 PM Development: RE: Multiple top modules for lint
I didn't patch the codes inside for it.
A temporary wrapper file is made outside of verilator and thrown with origin...
Kris Jeon
12:24 PM Development: RE: Multiple top modules for lint
Nice. Can you post the contributed patches back (including some test cases) please? Thanks Wilson Snyder
12:20 PM Development: RE: Multiple top modules for lint
I've done. Thanks again.
!https://raw.githubusercontent.com/poucotm/Links/master/image/SublimeLinter-Contrib-Veril...
Kris Jeon
11:37 AM Usage: RE: Verilate SystemVerilog RTL without a top module?
So the problem is you want to verilate something at top with interfaces poking out the top?
Typically when doing t...
Wilson Snyder

01/04/2019

06:51 PM Usage: Verilate SystemVerilog RTL without a top module?
I'm a new to using verilator and I am trying to use it to cross verify RTL with an architectural model. Our model is ... Justin Jones

01/03/2019

11:22 PM Usage: RE: Any way around: %Error-ASSIGNIN, w/o editing Verilog?
ASSIGNIN can be disabled just like a warning, using e.g. //verilator pragmas, vlt files, or command line - see the ma... Wilson Snyder
10:17 PM Usage: Any way around: %Error-ASSIGNIN, w/o editing Verilog?
I'm bumping into this error: @%Error-ASSIGNIN@, because some behavioral simulation libraries provided to me by my fou... David Banas

01/02/2019

11:10 PM Usage: RE: Compile errors with Mingw32 on fstapi.c
Can you create a patch to fix these, then send the result to "Tony Bybell" <bybell@rocketmail.com> so they can be fix... Wilson Snyder
12:26 PM Development: RE: Multiple top modules for lint
It is good idea to use a top wrapper. I'll have to try it.
Thanks!
Kris Jeon
11:02 AM Development: RE: Multiple top modules for lint
P.S. Looping in main() would be a mess and cause other problems. Looping outside by calling verilator many times is ... Wilson Snyder
11:01 AM Development: RE: Multiple top modules for lint
Yes.
Probably the easiest fix would be to inside the generated top wrapper instead instantiate every module found ...
Wilson Snyder
10:51 AM Development: RE: Multiple top modules for lint
But it is possible to call separately like this ...... Kris Jeon
09:56 AM Development: RE: Multiple top modules for lint
At present there must be a single top module, multiple ones are not supported even in lint-only.
Or if I misunders...
Wilson Snyder
09:48 AM Development: Multiple top modules for lint
Hi,
How can I easily modify codes to repeat multiple modules for --lint-only mode ?
Instead of repeating outside ...
Kris Jeon
12:19 PM Usage: RE: How to use SystemVerilog package syntax?
I understand it's not a friendly message, but unfortunately comes from bison not Verilator sources so isn't really ch... Wilson Snyder

01/01/2019

06:11 AM Usage: RE: No "#pragma omp ..." lines in generated C++ code when using `--threads 2`?
Verilator uses C++11 threads instead. Wilson Snyder
12:59 AM Usage: No "#pragma omp ..." lines in generated C++ code when using `--threads 2`?
I just tried the _--threads_ option: @--threads 2@. <br>
I was expecting to see some lines of the form:...
David Banas

12/30/2018

03:39 PM Usage: RE: Wait on rising edge from c++
Actually, there is only one first if() for clock signal per circuit and only waiting simulation processes for this cl... Michal Orsak

12/26/2018

04:02 PM Usage: RE: How to use SystemVerilog package syntax?
Sorry, this was a red herring.
The problem was that the class I was attempting to access hadn’t been defined, yet.
...
David Banas
04:33 AM Usage: RE: How to use SystemVerilog package syntax?
Er, what is the code it is complaining about? Wilson Snyder

12/25/2018

06:07 PM Usage: How to use SystemVerilog package syntax?
I'm having trouble using basic SystemVerilog package syntax.
I'm getting this error:...
David Banas

12/20/2018

11:54 AM Usage: RE: Wait on rising edge from c++
I suspect it will have trouble with larger designs where multiple if()'s are inserted, but give it a try.
Wilson Snyder

12/19/2018

05:37 PM Usage: RE: Wait on rising edge from c++
Thank you for fast fast responce.
You are right, it will not work as it is. But if we add read/write only restrict...
Michal Orsak
03:15 PM Usage: RE: Wait on rising edge from c++
Easiest is
new AstCStmt(nodep->fileline(), "ON_CHANGE()")
However as I noted earlier I think this ON_CHANGE a...
Wilson Snyder
03:09 PM Usage: RE: Wait on rising edge from c++
Hello, how do I add C macro call to AST?
If I use AstCFunc:...
Michal Orsak
02:48 AM Usage: Compile errors with Mingw32 on fstapi.c
Hi,
I'm getting errors on literals used in fstapi.c with the mingw32 g++ compiler (7.3.0) on Fedora 28. mingw64 g...
Richard Myers

12/17/2018

12:06 PM Usage: RE: Set timescale in model at runtime (ie. before first eval())?
You'd call tfp->set_time_unit(timescale). It's in VerilatedVcd, which is the base class of VerilatedVcdC.
The sim...
Wilson Snyder
07:35 AM Usage: RE: Set timescale in model at runtime (ie. before first eval())?
Hi,
I have a double with the time step, so would prefer to avoid the text conversion. I could do it and then call...
Richard Myers
04:24 AM Usage: RE: Set timescale in model at runtime (ie. before first eval())?
Great, thanks!
Richard
Richard Myers
02:10 AM Usage: RE: Set timescale in model at runtime (ie. before first eval())?
See VerilatedVcdC::set_time_unit and set_time_resolution, and the helper doubleToTimescale.
Wilson Snyder
01:24 AM Usage: Set timescale in model at runtime (ie. before first eval())?
Hi,
I've made a dynamic library from a Verilated model. The calling program calls the model at each time step, wh...
Richard Myers

12/08/2018

01:10 PM Usage: RE: $readmemh should apply relative paths to verilog file (not to verilator running folder)
Other simulators don't as far as I can tell, and the standard doesn't say so, so I think it's doing the right thing.
Wilson Snyder
08:28 AM Usage: $readmemh should apply relative paths to verilog file (not to verilator running folder)
I have a verilog file that reads a hex file in the same folder using $readmemh. So far so good, but if verilator is c... Jose Tejada
 

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