Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Activity

From 02/23/2019 to 03/24/2019

03/10/2019

04:16 PM Development: RE: trying to run the tests
See what was wrong, this should be fixed in git, thanks for the bug report & debugging.
Note you should cpan insta...
Wilson Snyder
06:57 AM Development: RE: trying to run the tests
I have tried that, can't see any changes. All the same. I have attached the LOG files. Hope it will be helpful Enzo Chi

03/08/2019

11:10 PM Usage: RE: Simulation slow down due to a large new block that's idle
If the logic is all on a clock and the clock is disabled you should not see a large change. Make sure there aren't a... Wilson Snyder
02:49 PM Usage: Simulation slow down due to a large new block that's idle
I've recently added a large new block into the simulation... and even though the block is completely idle in tests, t... Stan Sokorac

03/07/2019

04:07 PM Usage: RE: Trouble getting started with linting
:FACEPALM: Awesome - I even read about header guards while spinning myself in circles. Thank you! Charles Eddleston
12:32 PM Usage: RE: Trouble getting started with linting
Both test1 and test2 include iface.svh, so the interface is defined twice hence the warning. Put an include guard ar... Wilson Snyder
05:11 AM Usage: Trouble getting started with linting
Hello!
I'm trying to get basic lint check working and I'm hitting a wall on ~step 1. I'm trying to `include a verilo...
Charles Eddleston
12:30 PM Development: RE: trying to run the tests
Perhaps the perl IPC::Forker package is exiting early, is there something special about your system like weird securi... Wilson Snyder
04:45 AM Development: RE: trying to run the tests
That's all I got. Enzo Chi
12:00 AM Development: RE: trying to run the tests
The first lines are correct. Nothing at all after that?
Wilson Snyder

03/06/2019

10:04 PM Development: RE: trying to run the tests
I did the configuration with this command... Enzo Chi
03:35 PM Usage: RE: FST dumping 100x slower than VCD
Would it be also possible for your usage to use the Gtkwave "vcd2fst" utility? I regularly use it since it provides a... Jérémie Chabloz
03:25 PM Usage: error using verilatedvcdsc

i am putting forward an error which i am facing
../sc_main.cpp: In function ‘int sc_main(int, char**)’: ../sc_...
divyakumar shah

03/03/2019

07:59 AM Usage: RE: Multiple comma-separated declaration in one for-loop
I add 2 small files for this and this regression works fine. Also, t_for_comma_bad regression can be removed later.
...
Yu Sheng Lin

03/02/2019

12:54 PM Development: RE: detecting edges in an initial block
Verilator is a cycle based simulator, not an event based simulator, so this is unlikely to be supported anytime soon.... Wilson Snyder
10:53 AM Development: detecting edges in an initial block
Dear developers,
I was wondering if you could support the execution of the following code (which is supported by c...
Art. FR

02/28/2019

02:17 AM Usage: RE: Multiple comma-separated declaration in one for-loop
Thanks for this work, I need to spend some more time looking at the details of this, but for now I think the big thin... Wilson Snyder

02/27/2019

02:03 AM Usage: RE: How to show enum names in gtkwave?
Thanks! Results I hoped are showed!
Soya Ohnishi
01:48 AM Usage: RE: How to show enum names in gtkwave?
see t_trace_complex.v in the git repo, e.g.
typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t;
enumed_...
Wilson Snyder
12:46 AM Usage: RE: How to show enum names in gtkwave?
Thanks for your reply.
You said
> You have "metal" declared as a logic instead of newMetal type.
Do you mean I...
Soya Ohnishi

02/26/2019

11:25 PM Usage: RE: FST dumping 100x slower than VCD
David, Fixed documentation in git, thanks for the note.
Wilson Snyder
04:18 PM Usage: RE: How to show enum names in gtkwave?
You have "metal" declared as a logic instead of newMetal type.
Wilson Snyder
03:42 AM Usage: How to show enum names in gtkwave?
Hello.
I learned that verilator and gtkwave support enums from chisel3 mailinglist, so I tried to use this feature...
Soya Ohnishi
04:07 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
That is the link, yes. The assumption is you are already familiar with the general VPI as described in IEEE and othe... Wilson Snyder
04:02 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
Can you refer to the "VPI" section of the documentation as the following URL? If so, this introduction seems to be t... Yu Kai Liang
03:53 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
See the "VPI" section of the documentation. You should not need to look at or understand the C++ internal code to ge... Wilson Snyder
03:26 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
Yes, my problem is after calling the vpi_put_value method, how to affect a signal in Verilog that has been Verilated ... Yu Kai Liang
03:16 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
I assume by "in C++ model" you mean affect a signal in Verilog that has been Verilated into C++.
First, check ther...
Wilson Snyder
03:09 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
I don't know how to affect the value of the specified signal in C++ model after calling the vpi_put_value method. Yu Kai Liang
02:57 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
Please take a step back from the internals, what is broken or what problem are you having?
Wilson Snyder
02:33 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
I'm working on chisel-testers, and I've traced back to its test mechanism approach to calling the vpi_get_value and v... Yu Kai Liang
02:18 PM Usage: RE: About assigning values to C++ models and getting values(VPI)
What are you trying to do? Those internals are not something that you normally need to use, applications are expecte... Wilson Snyder
12:10 PM Usage: About assigning values to C++ models and getting values(VPI)
In the verilated_vpi.cpp file, the vpi_get_value and vpi_put_value methods respectively take values and assignments t... Yu Kai Liang

02/23/2019

06:07 PM Usage: RE: FST dumping 100x slower than VCD
I'm working on a similar issue, and noticed that the documentation says for benchmarking purposes, pass --x-initial=f... David Stanford
12:49 PM Usage: RE: Multiple comma-separated declaration in one for-loop
I implement the basic version for this feature based on v4.008.
Current code is changed significantly since later as...
Yu Sheng Lin
 

Also available in: Atom