Verilator

04/16/2019

09:48 PM Issue #1419 (Closed): --trace-fst documentation issue

Small documentation fix:
https://github.com/toddstrader/verilator-dev/tree/fst-doc-fix Todd Strader

04:26 PM Issue #1305: Error messages do not contain hierarchical information

I've posted the latest changes here:
https://github.com/toddstrader/verilator-dev/tree/mod_stack_trace
This now a... Todd Strader

04/15/2019

02:26 PM Issue #1418: Having trouble assigning signals of interfaces to regs within for loop

Hi Wilson,
We come across a Xilinx page that suggests having for loop inside always_comb helps to save runtime.
h... Junyi Xie

04/12/2019

08:54 PM Issue #1418: Having trouble assigning signals of interfaces to regs within for loop

This is reasonable.
Thanks for the quick reply by the way!
Junyi Xie

08:35 PM Issue #1418 (WillNotFix): Having trouble assigning signals of interfaces to regs within for loop

Verilator currently requires interface (or cell) references must be statically unrolled. This is currently a fairly f... Wilson Snyder

06:50 PM Issue #1418 (WillNotFix): Having trouble assigning signals of interfaces to regs within for loop

Hi Wilson,
I experienced errors when I tried to assign signals of an interfaces array to 2-d regs.
Attached are e... Junyi Xie

05:19 PM Issue #1305: Error messages do not contain hierarchical information

V3Number started long ago as a relatively independent thing without concept of nodes, but don't see a reason it has t... Wilson Snyder

04:18 PM Issue #1305: Error messages do not contain hierarchical information

I've posted a proposed change for this here:
https://github.com/toddstrader/verilator-dev/tree/mod_stack_trace
On... Todd Strader

04/11/2019

12:52 AM Issue #1417 (Resolved): FST regression tests fail instead of skip if fst2vcd isn't installed

Fixed in git towards 4.014.
Wilson Snyder

04/10/2019

03:15 PM Issue #1417 (Closed): FST regression tests fail instead of skip if fst2vcd isn't installed

... Todd Strader

04/06/2019

01:20 AM Issue #1415 (Resolved): Verilator generates calls to an undefined function named: VL_SHIFTR_QQW

Thanks again for the patch.
Pushed to git towards 4.014.
Wilson Snyder

04/05/2019

01:29 PM Issue #1415 (Closed): Verilator generates calls to an undefined function named: VL_SHIFTR_QQW

Verilator is generating calls to a undefined function named VL_SHIFTR_QQW.
This bug is nearly identical to that re... Larry Lee

04/03/2019

03:37 PM Issue #1414 (Duplicate): Multi dimensional variable in function causing issues

Hi,
I added a small example of a structure that causes issues in our codebase. We use a function to calculate a lo... Johan Wouters

04/02/2019

10:25 PM Issue #1413 (Resolved): Wrong printf/scanf format specifiers used for MinGW targets

Excellent, thanks for the work & patch.
Fixed in git towards 4.014.
Wilson Snyder

12:23 PM Issue #1413 (Closed): Wrong printf/scanf format specifiers used for MinGW targets

Modern MinGW C runtime versions (starting from GCC 6)
have switched to C99/C++11 compliant printf/scanf
format spec... Sergey Kvachonok

03/30/2019

06:10 PM Issue #1336: Verilator installation make error

I ran into similar issues building verilator on Linux Mint and Ubuntu, they seem to exist on RedHat & Suse as well is... Dwayne Jackson

03/29/2019

12:20 AM Issue #1412 (Resolved): Verilator generates calls to an undefined function named: VL_SHIFTL_QQW

Thanks for the patch, very close, just had to make a minor change in that it needs to be passed QData input to avoid ... Wilson Snyder

03/28/2019

06:11 PM Issue #1412: Verilator generates calls to an undefined function named: VL_SHIFTL_QQW

https://github.com/llee454/verilator Larry Lee

06:11 PM Issue #1412 (Closed): Verilator generates calls to an undefined function named: VL_SHIFTL_QQW

Verilator is generating calls to a undefined function named VL_SHIFTL_QQW.
I've found that defining this function ... Larry Lee

03/27/2019

11:40 AM Issue #1411 (Resolved): # comments support in .mem files

Makes sense, love getting patches with requests!
Fixed in git towards 4.013.
Wilson Snyder

03/26/2019

04:53 PM Issue #1411 (Closed): # comments support in .mem files

Hello,
I am using the excellent tool SRecord v1.64 (http://srecord.sourceforge.net/) to generate .mem files when com... Frederic Requin

03/24/2019

01:15 AM Issue #1383 (Closed): Support SystemVerilog void casts & warn if not present

In 4.012.
Wilson Snyder

01:15 AM Issue #1384 (Closed): File-extension language option not consistently applied

In 4.012.
Wilson Snyder

01:15 AM Issue #1396 (Closed): Verilator random number generated seeded with lrand48(), which isn't determ...

In 4.012.
Wilson Snyder

01:15 AM Issue #1400 (Closed): Bug: verilator sometimes fails to detect electrical short

In 4.012.
Wilson Snyder

01:15 AM Issue #1406 (Closed): Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion i...

In 4.012.
Wilson Snyder

01:15 AM Verilator 4.012 Released

Verilator 4.012 2019-3-23
*** Add +verilator+seed, bug1396. [Stan Sokorac]
*** Support $fread. [Leendert v... Wilson Snyder

03/21/2019

11:20 AM Issue #1402: Compile verilator to webassembly

>But you also need to apt-get install libfl-dev (https://packages.ubuntu.com/bionic/amd64/libfl-dev/filelist).
Ubu... Wilson Snyder

07:13 AM Issue #1402: Compile verilator to webassembly

Under Ubuntu 18.04LTS (bionic), the likely issue is that [[Installing]] implies the dependencies are:... Tyrel Newton