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Activity

From 06/08/2019 to 07/07/2019

07/07/2019

12:41 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
Thank you very much for the quick reply toby matthews
12:03 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
Yes, you need to include the internal header. Typically also include the main header:
#include "Vram.h"
#in...
Wilson Snyder
09:31 AM Usage: use enum from a sv module in c++ testbench using /*verilator_public*/
Hello all,
I would like to get some help to use typedef enums from a module. I found this: https://www.veripool.or...
toby matthews

07/04/2019

03:59 PM Usage: RE: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
Which language are you asking about writing these in?
If C++, then I'd use C++11 threads.
If Verilog, then usin...
Wilson Snyder

07/03/2019

03:48 PM Usage: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...
Udi Finkelstein

06/29/2019

03:34 PM Development: RE: Error on indexing the multiple dimensional array (MDA)
Sorry, this got misplaced for a while as wasn't in the issues list.
Your proposed fix is in the right spot, but en...
Wilson Snyder

06/26/2019

09:40 AM Usage: RE: Any chance to use Verilator together with Icuras?
Verilator has plans to add "embedding" of a model in another simulator, but this is not ready yet (there is another o... Wilson Snyder
08:59 AM Usage: Any chance to use Verilator together with Icuras?
With Verilator to compile the DUT part and have Irucas handle the testbench which might be UMV based. Yong Fu

06/20/2019

11:28 AM Usage: RE: How could I use other ways to achieve the fork join statement
The problem here isn't likely the fork/join but that I think the implication from your question is that your receive/... Wilson Snyder
09:19 AM Usage: How could I use other ways to achieve the fork join statement
The verilator will throw an error when I use the fork and join statement. For example:... Zhiyuan Ning

06/12/2019

11:06 AM Usage: RE: Verilator detect problem of '@'
... Wilson Snyder
02:24 AM Usage: RE: Verilator detect problem of '@'
How could I refactor such tasks (time pass) to look like synthesizable code? Could you give me an example? Zhiyuan Ning
02:04 AM Usage: RE: Verilator detect problem of '@'
Verilator doesn't support arbitrary event expressions, sorry.
Specifically, tasks can't have time pass and gener...
Wilson Snyder
01:31 AM Usage: Verilator detect problem of '@'
I write a .sv task inside an interface like:
task receive ();

assert property (@(posedge data)) ;

endtas...
Zhiyuan Ning
 

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