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Activity

From 06/22/2019 to 07/21/2019

07/21/2019

11:45 AM Development: RE: One eval() method per clock domain ?
Multiple evals would save some branch instructions. There's two problems though, first is any logic downstream which... Wilson Snyder
10:05 AM Development: One eval() method per clock domain ?
Hello,
in multiple clock domains designs, I am wondering if it would be more efficient to have one eval() method p...
Frederic Requin

07/13/2019

11:15 AM Usage: RE: How to disable MULTITOP?
Note the code in git and next version 4.018 will allow multiple top files - see the documentation.
Wilson Snyder

07/07/2019

12:41 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
Thank you very much for the quick reply toby matthews
12:03 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
Yes, you need to include the internal header. Typically also include the main header:
#include "Vram.h"
#in...
Wilson Snyder
09:31 AM Usage: use enum from a sv module in c++ testbench using /*verilator_public*/
Hello all,
I would like to get some help to use typedef enums from a module. I found this: https://www.veripool.or...
toby matthews

07/04/2019

03:59 PM Usage: RE: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
Which language are you asking about writing these in?
If C++, then I'd use C++11 threads.
If Verilog, then usin...
Wilson Snyder

07/03/2019

03:48 PM Usage: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...
Udi Finkelstein

06/29/2019

03:34 PM Development: RE: Error on indexing the multiple dimensional array (MDA)
Sorry, this got misplaced for a while as wasn't in the issues list.
Your proposed fix is in the right spot, but en...
Wilson Snyder

06/26/2019

09:40 AM Usage: RE: Any chance to use Verilator together with Icuras?
Verilator has plans to add "embedding" of a model in another simulator, but this is not ready yet (there is another o... Wilson Snyder
08:59 AM Usage: Any chance to use Verilator together with Icuras?
With Verilator to compile the DUT part and have Irucas handle the testbench which might be UMV based. Yong Fu
 

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