From 06/23/2019 to 07/22/2019
- 11:45 AM Development: RE: One eval() method per clock domain ?
- Multiple evals would save some branch instructions. There's two problems though, first is any logic downstream which...
in multiple clock domains designs, I am wondering if it would be more efficient to have one eval() method p...
- 11:15 AM Usage: RE: How to disable MULTITOP?
- Note the code in git and next version 4.018 will allow multiple top files - see the documentation.
- 12:41 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
- Thank you very much for the quick reply
- 12:03 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
- Yes, you need to include the internal header. Typically also include the main header:
- Hello all,
I would like to get some help to use typedef enums from a module. I found this: https://www.veripool.or...
- 03:59 PM Usage: RE: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
- Which language are you asking about writing these in?
If C++, then I'd use C++11 threads.
If Verilog, then usin...
- I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...
- 03:34 PM Development: RE: Error on indexing the multiple dimensional array (MDA)
- Sorry, this got misplaced for a while as wasn't in the issues list.
Your proposed fix is in the right spot, but en...
- 09:40 AM Usage: RE: Any chance to use Verilator together with Icuras?
- Verilator has plans to add "embedding" of a model in another simulator, but this is not ready yet (there is another o...
- With Verilator to compile the DUT part and have Irucas handle the testbench which might be UMV based.
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