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Activity

From 06/30/2019 to 07/29/2019

07/29/2019

11:45 AM Usage: RE: A strange code generated from parametric module.
Thanks for reply, Wilson. I'd like to understand why Verilator converts verilog's 3-bit port into 32-bit port in Syst... Slava B
11:17 AM Usage: RE: A strange code generated from parametric module.
I assume what you really mean is you got a uint32_t. Verilator does this because it's several times faster than usin... Wilson Snyder
06:32 AM Usage: A strange code generated from parametric module.
Hello,
I was asked to convert a big Verilog project to SystemC. I'm a novice in Verilog and cannot explain the res...
Slava B

07/27/2019

10:23 AM Usage: RE: Error: verilator threw signal 2
What was all of the output?
Wilson Snyder
08:05 AM Usage: Error: verilator threw signal 2
I ran into this error when I'm running RTL simulation of SiFive Coreip Evaluation Dev Kit. How to solve this ??
Yifei He

07/25/2019

11:27 PM Development: RE: PSA: rr is amazing
Neat, I hadn't seen gdbui before. I'll have to check that out.
I'm not sure about your issues. I've used rr to d...
Todd Strader
10:30 PM Development: RE: PSA: rr is amazing
Nice. It looks like it can run under gdbgui which is worth trying as that would be a great pairing.
After an rr r...
Wilson Snyder
02:44 PM Development: PSA: rr is amazing
I've been using rr instead of (on top of?) gdb to debug Verilator and it's pretty awesome. It records the execution ... Todd Strader

07/21/2019

11:45 AM Development: RE: One eval() method per clock domain ?
Multiple evals would save some branch instructions. There's two problems though, first is any logic downstream which... Wilson Snyder
10:05 AM Development: One eval() method per clock domain ?
Hello,
in multiple clock domains designs, I am wondering if it would be more efficient to have one eval() method p...
Frederic Requin

07/13/2019

11:15 AM Usage: RE: How to disable MULTITOP?
Note the code in git and next version 4.018 will allow multiple top files - see the documentation.
Wilson Snyder

07/07/2019

12:41 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
Thank you very much for the quick reply toby matthews
12:03 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
Yes, you need to include the internal header. Typically also include the main header:
#include "Vram.h"
#in...
Wilson Snyder
09:31 AM Usage: use enum from a sv module in c++ testbench using /*verilator_public*/
Hello all,
I would like to get some help to use typedef enums from a module. I found this: https://www.veripool.or...
toby matthews

07/04/2019

03:59 PM Usage: RE: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
Which language are you asking about writing these in?
If C++, then I'd use C++11 threads.
If Verilog, then usin...
Wilson Snyder

07/03/2019

03:48 PM Usage: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...
Udi Finkelstein
 

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