From 06/30/2019 to 07/29/2019
- 11:45 AM Usage: RE: A strange code generated from parametric module.
- Thanks for reply, Wilson. I'd like to understand why Verilator converts verilog's 3-bit port into 32-bit port in Syst...
- 11:17 AM Usage: RE: A strange code generated from parametric module.
- I assume what you really mean is you got a uint32_t. Verilator does this because it's several times faster than usin...
I was asked to convert a big Verilog project to SystemC. I'm a novice in Verilog and cannot explain the res...
- 10:23 AM Usage: RE: Error: verilator threw signal 2
- What was all of the output?
- I ran into this error when I'm running RTL simulation of SiFive Coreip Evaluation Dev Kit. How to solve this ??
- 11:27 PM Development: RE: PSA: rr is amazing
- Neat, I hadn't seen gdbui before. I'll have to check that out.
I'm not sure about your issues. I've used rr to d...
- 10:30 PM Development: RE: PSA: rr is amazing
- Nice. It looks like it can run under gdbgui which is worth trying as that would be a great pairing.
After an rr r...
- I've been using rr instead of (on top of?) gdb to debug Verilator and it's pretty awesome. It records the execution ...
- 11:45 AM Development: RE: One eval() method per clock domain ?
- Multiple evals would save some branch instructions. There's two problems though, first is any logic downstream which...
in multiple clock domains designs, I am wondering if it would be more efficient to have one eval() method p...
- 11:15 AM Usage: RE: How to disable MULTITOP?
- Note the code in git and next version 4.018 will allow multiple top files - see the documentation.
- 12:41 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
- Thank you very much for the quick reply
- 12:03 PM Usage: RE: use enum from a sv module in c++ testbench using /*verilator_public*/
- Yes, you need to include the internal header. Typically also include the main header:
- Hello all,
I would like to get some help to use typedef enums from a module. I found this: https://www.veripool.or...
- 03:59 PM Usage: RE: Lightweightlibrary for writing multiple parallel Verilator testbench drivers?
- Which language are you asking about writing these in?
If C++, then I'd use C++11 threads.
If Verilog, then usin...
- I want to write a testbench for a large SV RTL codebase.
The code is currently simulated via a Verilog testbench run...
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