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Activity

From 07/23/2019 to 08/21/2019

08/21/2019

11:52 PM Usage: RE: Incremental verilate on large designs?
Yes, multiple sub-evals are needed. The assumption is the sub-module verilation will determine many combo sub-evals e... Wilson Snyder
08:12 PM Usage: RE: Incremental verilate on large designs?
Revisiting this... one thing that seems problematic to me about breaking up the design into multiple ones and then cr... Stan Sokorac
12:03 AM Usage: RE: Increasing performance in a moderately clock gated design
The Clkgate stage was experimental fir adding gating (not your case I think) and is not currently enabled as slowed t... Wilson Snyder

08/18/2019

01:14 AM Development: RE: Verilator fails to warn/error on procedural assignment to wire
In order to raise the warning for port, I've changed like the following:
In 'V3ParseGrammar.cpp'...
Kris Jeon

08/15/2019

06:09 PM Usage: Increasing performance in a moderately clock gated design
I've been looking at speeding up verilator for a design. A few months ago I added in a large module that is mostly id... James Connolly

08/09/2019

07:38 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
> That is, the generation of a protected model is NOT elaborating and compiling to a representation that supports dif... Todd Strader

08/08/2019

10:03 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
Thanks, now I understand, you're not really directly wanting runtime
parameters. You want wanting protected models a...
Wilson Snyder
12:33 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
> Can you describe why this is needed
For example, Xilinx provides the simulation model of its DSP as encrypted Veri...
Todd Strader

08/07/2019

09:57 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
P.S. Adding a hash of symbols could easily be added as an option in V3Name stage, and there's already a cryto hash in... Wilson Snyder
09:55 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
I am very skeptical on constructor-time parameters as a feature, both in
terms of the technical problems involved (w...
Wilson Snyder
11:04 AM Development: RFC: DPI encapsulated Verilog instead of encryption
Please see:
https://github.com/toddstrader/dpi-compile
Any comments are welcomed, but I'd specifically like to as...
Todd Strader

07/29/2019

11:45 AM Usage: RE: A strange code generated from parametric module.
Thanks for reply, Wilson. I'd like to understand why Verilator converts verilog's 3-bit port into 32-bit port in Syst... Slava B
11:17 AM Usage: RE: A strange code generated from parametric module.
I assume what you really mean is you got a uint32_t. Verilator does this because it's several times faster than usin... Wilson Snyder
06:32 AM Usage: A strange code generated from parametric module.
Hello,
I was asked to convert a big Verilog project to SystemC. I'm a novice in Verilog and cannot explain the res...
Slava B

07/27/2019

10:23 AM Usage: RE: Error: verilator threw signal 2
What was all of the output?
Wilson Snyder
08:05 AM Usage: Error: verilator threw signal 2
I ran into this error when I'm running RTL simulation of SiFive Coreip Evaluation Dev Kit. How to solve this ??
Yifei He

07/25/2019

11:27 PM Development: RE: PSA: rr is amazing
Neat, I hadn't seen gdbui before. I'll have to check that out.
I'm not sure about your issues. I've used rr to d...
Todd Strader
10:30 PM Development: RE: PSA: rr is amazing
Nice. It looks like it can run under gdbgui which is worth trying as that would be a great pairing.
After an rr r...
Wilson Snyder
02:44 PM Development: PSA: rr is amazing
I've been using rr instead of (on top of?) gdb to debug Verilator and it's pretty awesome. It records the execution ... Todd Strader
 

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