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Activity

From 07/31/2019 to 08/29/2019

08/27/2019

11:28 PM Usage: RE: Increasing performance in a moderately clock gated design
As to the for loops, it looks like a new optimization should be added to make this code perform better, e.g. a o_gnt1... Wilson Snyder
08:39 PM Development: RE: Verilator fails to warn/error on procedural assignment to wire
Further discussions under bug1369.
Wilson Snyder
10:53 AM Usage: RE: Unsupported: wor
Verilator doesn't support all of the Verilog language. xor is not supported as it says.
Wilson Snyder
08:13 AM Usage: Unsupported: wor
Hello,
I'm trying to convert a big project and receive the following message: *Unsupported: wor*. As far as I unde...
Slava B

08/22/2019

05:43 PM Usage: RE: Increasing performance in a moderately clock gated design
Nasty combinational logic with nested loops seems to be where I'm sinking most of my cycles (~30% of time). Attached ... James Connolly

08/21/2019

11:52 PM Usage: RE: Incremental verilate on large designs?
Yes, multiple sub-evals are needed. The assumption is the sub-module verilation will determine many combo sub-evals e... Wilson Snyder
08:12 PM Usage: RE: Incremental verilate on large designs?
Revisiting this... one thing that seems problematic to me about breaking up the design into multiple ones and then cr... Stan Sokorac
12:03 AM Usage: RE: Increasing performance in a moderately clock gated design
The Clkgate stage was experimental fir adding gating (not your case I think) and is not currently enabled as slowed t... Wilson Snyder

08/18/2019

01:14 AM Development: RE: Verilator fails to warn/error on procedural assignment to wire
In order to raise the warning for port, I've changed like the following:
In 'V3ParseGrammar.cpp'...
Kris Jeon

08/15/2019

06:09 PM Usage: Increasing performance in a moderately clock gated design
I've been looking at speeding up verilator for a design. A few months ago I added in a large module that is mostly id... James Connolly

08/09/2019

07:38 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
> That is, the generation of a protected model is NOT elaborating and compiling to a representation that supports dif... Todd Strader

08/08/2019

10:03 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
Thanks, now I understand, you're not really directly wanting runtime
parameters. You want wanting protected models a...
Wilson Snyder
12:33 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
> Can you describe why this is needed
For example, Xilinx provides the simulation model of its DSP as encrypted Veri...
Todd Strader

08/07/2019

09:57 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
P.S. Adding a hash of symbols could easily be added as an option in V3Name stage, and there's already a cryto hash in... Wilson Snyder
09:55 PM Development: RE: RFC: DPI encapsulated Verilog instead of encryption
I am very skeptical on constructor-time parameters as a feature, both in
terms of the technical problems involved (w...
Wilson Snyder
11:04 AM Development: RFC: DPI encapsulated Verilog instead of encryption
Please see:
https://github.com/toddstrader/dpi-compile
Any comments are welcomed, but I'd specifically like to as...
Todd Strader
 

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