From 08/28/2019 to 09/26/2019
- Hi all,
My design uses a library file with an $fopen call like this:...
- 10:02 PM Usage: RE: Increasing performance in a moderately clock gated design
- Thanks for the pointer to BOLT. It would be very interesting ifs you could create a before and after istream heat ma...
- 03:27 PM Usage: RE: Increasing performance in a moderately clock gated design
- Thanks for the tips here Wilson; I massaged some of the arbiters to be optimized by V3Table and got great speedup wit...
- 02:00 PM Usage: RE: Error on 2D array of interface
- Hi Wilson,
thanks for the quick answer, indeed this is part of *APU cluster* (auxiliary processing unit from PULP-...
- 01:38 PM Usage: RE: Error on 2D array of interface
- This is unsupported by mistake, that is a bug in translating the grammar. Even Verilog-Perl which is the basis for th...
- Hi everyone,
I would like to know if Verilator 4.018 supports *2D array* of interfaces like the one below:
- 01:01 PM Usage: RE: any chance of gettting deassign working?
- There wasn't a suggested change to Verilator, the assumption is the user (you) will make a substitute module. Sorry.
- 12:55 PM Usage: RE: any chance of gettting deassign working?
- Any news related to the substitution story mentioned by Wilson? I cannot verilate a project due to usage of deassign ...
- 11:39 AM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
- Also, I'm not sure how vcs will accept DPI objects. By default --dpi-protect will produce a static library (.a) but ...
- 08:22 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
- So you're a void-the-warranty kind of person? I respect that.
To be clear, this branch is passing CI including a ...
- 08:09 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
- Todd, I downloaded the link. Verilator version doesn't have all the familiar makefiles and configuration. How do I ...
- 05:32 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
- Awesome! Thank you Todd. I will check it out and report back. If it works good enough to re-run the same simulati...
- 02:52 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
- I don't know the answer to #1, but for #2 you should be able to use this in-progress feature once it is ready:
- In my vcs simulation model, for certain, simulation content, I see majority of simulation time spent in the microcont...
- 11:24 AM Usage: RE: Single-bit signals represented as VL_SIG8
- It's because that is an order of magnitude faster. See the Verilator manual for options on representing SC signals.
I was curious why single-bit signals are represented in verilated SystemC code as:
- 10:40 AM Usage: RE: Conversion of a hierarchical design
- By the way, sw debugging became less relevant when I found out that it is possible to add internal Verilog signals to...
- 01:48 PM Usage: RE: Conversion of a hierarchical design
- I understand your point. If the compiled design and test-bench start working properly from the fist moment, everythin...
- 12:58 PM Usage: RE: Conversion of a hierarchical design
- Verilator basically compiles into SystemC, versus just translating to something debuggable.
However you can use "-...
First of all, thanks for the great tool. I took a big design, written in Verilog, and converted it to SystemC ...
- 01:30 PM Usage: RE: Verilator should have converted inout ports to input/output pairs.
- Thanks for explanations!
- 11:02 AM Usage: RE: Verilator should have converted inout ports to input/output pairs.
- The documentation should be updated, currently what it does for __en etc is only in the internals not top pins. One w...
As far as I understand from the documentation, Verilator should convert inout ports to input/output pairs. Is ...
- 11:02 AM Development: RE: sc_inout and tristate support
- Unfortunately not. One workaround is to make a wrapper module that does the conversion.
- 07:47 AM Development: RE: sc_inout and tristate support
Is there any update on this very important feature?
- 11:24 PM Development: RE: Building Verilator with Bazel
- Quick update for anyone who's come across this thread: I've improved the Bazel rules such that they no longer require...
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