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Activity

From 08/29/2019 to 09/27/2019

09/27/2019

08:51 AM Usage: recursive function support?
We have download a design from Github. This design can run correctly in VCS. But verilator compile hang.
https://...
Yong Fu
03:37 AM Usage: RE: Workaround for unsupported fopen in verilog library
Are you trying to simulate or just lint? If simulate this can't be ignored as it won't work, & perhaps contribute a ... Wilson Snyder

09/26/2019

09:30 PM Usage: Workaround for unsupported fopen in verilog library
Hi all,
My design uses a library file with an $fopen call like this:...
Ted X

09/12/2019

10:02 PM Usage: RE: Increasing performance in a moderately clock gated design
Thanks for the pointer to BOLT. It would be very interesting ifs you could create a before and after istream heat ma... Wilson Snyder
03:27 PM Usage: RE: Increasing performance in a moderately clock gated design
Thanks for the tips here Wilson; I massaged some of the arbiters to be optimized by V3Table and got great speedup wit... James Connolly
02:00 PM Usage: RE: Error on 2D array of interface
Hi Wilson,
thanks for the quick answer, indeed this is part of *APU cluster* (auxiliary processing unit from PULP-...
Ânderson Ignacio Da Silva
01:38 PM Usage: RE: Error on 2D array of interface
This is unsupported by mistake, that is a bug in translating the grammar. Even Verilog-Perl which is the basis for th... Wilson Snyder
01:19 PM Usage: Error on 2D array of interface
Hi everyone,
I would like to know if Verilator 4.018 supports *2D array* of interfaces like the one below:
!arr...
Ânderson Ignacio Da Silva

09/11/2019

01:01 PM Usage: RE: any chance of gettting deassign working?
There wasn't a suggested change to Verilator, the assumption is the user (you) will make a substitute module. Sorry.
Wilson Snyder
12:55 PM Usage: RE: any chance of gettting deassign working?
Any news related to the substitution story mentioned by Wilson? I cannot verilate a project due to usage of deassign ... Slava B
11:39 AM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
Also, I'm not sure how vcs will accept DPI objects. By default --dpi-protect will produce a static library (.a) but ... Todd Strader

09/10/2019

08:22 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
So you're a void-the-warranty kind of person? I respect that.
To be clear, this branch is passing CI including a ...
Todd Strader
08:09 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
Todd, I downloaded the link. Verilator version doesn't have all the familiar makefiles and configuration. How do I ... Oleg Rodionov
05:32 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
Awesome! Thank you Todd. I will check it out and report back. If it works good enough to re-run the same simulati... Oleg Rodionov
02:52 PM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
I don't know the answer to #1, but for #2 you should be able to use this in-progress feature once it is ready:
https...
Todd Strader
02:16 PM Usage: Using vcs to simulate design with multiple verilated uC cores?
In my vcs simulation model, for certain, simulation content, I see majority of simulation time spent in the microcont... Oleg Rodionov

09/09/2019

11:24 AM Usage: RE: Single-bit signals represented as VL_SIG8
It's because that is an order of magnitude faster. See the Verilator manual for options on representing SC signals.
Wilson Snyder
10:19 AM Usage: Single-bit signals represented as VL_SIG8
Hi,
I was curious why single-bit signals are represented in verilated SystemC code as:
...
Slava B
10:40 AM Usage: RE: Conversion of a hierarchical design
By the way, sw debugging became less relevant when I found out that it is possible to add internal Verilog signals to... Slava B

09/04/2019

01:48 PM Usage: RE: Conversion of a hierarchical design
I understand your point. If the compiled design and test-bench start working properly from the fist moment, everythin... Slava B
12:58 PM Usage: RE: Conversion of a hierarchical design
Verilator basically compiles into SystemC, versus just translating to something debuggable.
However you can use "-...
Wilson Snyder
11:51 AM Usage: Conversion of a hierarchical design
Hi,
First of all, thanks for the great tool. I took a big design, written in Verilog, and converted it to SystemC ...
Slava B

09/03/2019

01:30 PM Usage: RE: Verilator should have converted inout ports to input/output pairs.
Thanks for explanations! Slava B
11:02 AM Usage: RE: Verilator should have converted inout ports to input/output pairs.
The documentation should be updated, currently what it does for __en etc is only in the internals not top pins. One w... Wilson Snyder
08:27 AM Usage: Verilator should have converted inout ports to input/output pairs.
Hi,
As far as I understand from the documentation, Verilator should convert inout ports to input/output pairs. Is ...
Slava B
11:02 AM Development: RE: sc_inout and tristate support
Unfortunately not. One workaround is to make a wrapper module that does the conversion.
E.g.
module wrap;
...
Wilson Snyder
07:47 AM Development: RE: sc_inout and tristate support
Hi,
Is there any update on this very important feature?
Regards,
Slava
Slava B

08/31/2019

11:24 PM Development: RE: Building Verilator with Bazel
Quick update for anyone who's come across this thread: I've improved the Bazel rules such that they no longer require... Kevin Kiningham
 

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