Activity

From 10/11/2019 to 11/09/2019

11:58 AM Usage: RE: Testbench patterns to run N cycles ?: It finishes when there's a $finish, that's not really a signal.
Anyhow the example you point to should have s $fin... Wilson Snyder
11:50 AM Usage: Testbench patterns to run N cycles ?: Hello,
as I understand from the example sim_main.cc replaces the testbench.
The main loop stops when it receives ... Patrick Mulder
10:00 AM Installation: RE: Windows MinGW/Msys based build: Thanks, yes that works:
pacman -S mingw-w64-x86_64-verilator
Also, thanks for the additional pointers. Patrick Mulder
12:11 AM Installation: RE: Windows MinGW/Msys based build: As I said before, you shouldn't put /usr/include on the path, it will break everything. The easy thing to do is just ... Patrick Stewart

09:08 PM Installation: RE: Windows MinGW/Msys based build: In config.log there is already this:... Patrick Mulder
09:03 PM Installation: RE: Windows MinGW/Msys based build: I tried:
export CPPFLAGS=-I/usr/include... Patrick Mulder

11:26 AM Development: RE: Anywhere to find the description of cycle based simulator: Verilator figures out the logic graph of the code, basically as a cone, and starts from inputs evaluating what that n... Wilson Snyder
06:49 AM Development: RE: Anywhere to find the description of cycle based simulator: Or simply evaluate twice without advance the time? Yong Fu
05:48 AM Development: RE: Anywhere to find the description of cycle based simulator: Thanks Wilson.
The general understand of the CBS algorithm is:
1. simulate all combinational elements;
2. s... Yong Fu

05:46 PM Installation: RE: Windows MinGW/Msys based build: In msys2 you can just do "pacman -S mingw-w64-x86_64-verilator", there's already a package. You can see how it's buil... Patrick Stewart
02:58 AM Installation: RE: Windows MinGW/Msys based build: Given I see /mingw64/include on your command line I think your compiler isn't looking in /usr/include, e.g. where fle... Wilson Snyder
02:44 AM Usage: RE: Multiple comma-separated declaration in one for-loop: Sorry, think this got lost, I suggest:
1. File a bug so I don't forget :)
2. The code needs to support the mult... Wilson Snyder
02:37 AM Development: RE: enhancement to support SystemVerilog for loop multiple vars: Hmm, there was some work on this that seems to have gotten lost in the cracks.
https://www.veripool.org/boards/2/t... Wilson Snyder

03:11 PM Development: enhancement to support SystemVerilog for loop multiple vars: Hi,
I would like to start using Verilator more generally at my company and have found v4.020 supports
almost all ... Jon Stahl
09:28 AM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?: I'm not entirely sure, but it sounds like you're still on my development branch as we renamed the feature to --protec... Todd Strader
03:52 AM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?: Todd, I was able to compile my core with -dpi-protect flag. I do see static library being generated, but I don't see ... Oleg Rodionov
08:48 AM Installation: RE: CMake based build?: thanks, moving the discussion to a new thread. Patrick Mulder
08:47 AM Installation: Windows MinGW/Msys based build: Hello,... Patrick Mulder

09:40 PM Installation: RE: CMake based build?: Can you please attach a complete build log?
Most likely your flex didn't get installed correctly or something, a... Wilson Snyder
12:00 PM Development: RE: Anywhere to find the description of cycle based simulator: This isn't well documented, certainly something for us to improve.
Basically it works as you would expect gates to... Wilson Snyder
07:22 AM Development: Anywhere to find the description of cycle based simulator: In the following example, I can tell the event schedule and evaluation steps in a event based simulator. But for Veri... Yong Fu

01:02 PM Installation: RE: CMake based build?: One problem I get for the pacman build is this:
In file included from ../V3ParseLex.cpp:36:0:
V3Lexer_pregen.yy.c... Patrick Mulder
12:49 PM Installation: RE: CMake based build?: Thanks - ok, I see this Gist works fine with a MinGW shell:
https://gist.github.com/sgherbst/036456f807dc8aa84ffb2... Patrick Mulder
12:39 PM Installation: RE: CMake based build?: The git version, which is not yet released, supports using CMake for *verilated* modules, thanks to Patrick Stewart e... Wilson Snyder
12:28 PM Installation: CMake based build?: Hello,
I am new to Verilator but it looks interesting to learn and explore digital designs. I was looking at GnuCa... Patrick Mulder
11:25 AM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?: Interesting, but not unlikely as lots of baggage with SystemC. Would you be able to run the --dpi-protect benchmark ... Wilson Snyder
05:33 AM Usage: RE: Using vcs to simulate design with multiple verilated uC cores?: I was able to replace verilated uC core into my RTL design and simulate with VCS. I did following steps:
1. Verilat... Oleg Rodionov

06:41 PM Development: RE: Adding foreign module support to Verilator: Thanks! Will check that out. I definitely need trace (often that is the entire point), and at least in some cases com... Xavier Delacour
12:18 PM Development: RE: Adding foreign module support to Verilator: Also, please note that --protect-lib (just like normal Verilator compiles) requires that your embedded module's param... Todd Strader
11:53 AM Development: RE: Adding foreign module support to Verilator: We've recently added --protect-lib for embedding protected IP (instead of using encrypted RTL):
https://www.veripool... Todd Strader

05:16 PM Development: RE: Adding foreign module support to Verilator: I haven’t had the time to wrap this up, though I still have a need for it and would like to see it happen. Basically ... Xavier Delacour
04:40 PM Usage: RE: verilator include: IGNINC isn't a (mainline) Verilator warning. You must be using Verilator code you locally modified, so I can't know ... Wilson Snyder
04:32 PM Usage: verilator include: Hi,
I'v got a question about linting verilog project with verilator on ubuntu.
I'v got 2 files:
1)top.sv
<pre... alex al

09:00 PM Development: RE: Adding foreign module support to Verilator: Has any further progress been made on this? I think it would be a very useful feature! Conor McCullough

11:46 PM Development: RE: Requiring C++11 compiler: Don, thanks for the update. For now you're ok, current thinking is to require C+11 starting somewhere from 6 months ... Wilson Snyder
03:24 PM Development: RE: Requiring C++11 compiler: I'm using Verilator (4.018 currently) on a corporate RHEL 6.9 system (gcc 4.4.7). We're a mix of RHEL 6.x and transit... Don Owen
10:41 PM Usage: RE: FST dumping 100x slower than VCD: Added bug1566 so this is tracked.
Wilson Snyder

09:27 PM Usage: RE: Reduce Compile Memory: Solved this by switching to clang, which ended up being 10x faster. GCC required creating a monster large file, which... Kevin Hurd

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