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Activity
From 10/19/2019 to 11/17/2019
11/17/2019
- 06:39 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- Wilson Snyder wrote:
> All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of... - 11:42 AM Issue #1605: for loop initialisation clause skipped
- Thanks for fixing it so quickly.
- 11:36 AM Issue #1604: Unknown node in split color() map on empty if
- Thanks for fixing it. I had not attached any significance to them being unused; however, there are three instances o...
- 09:58 AM Issue #1606 (Resolved): Complete string methods (starter project)
- Implement the built-in string methods that are remaining:
- atobin, atohex, atoi, atooct, atoreal: Become a scanf....
11/16/2019
- 10:24 PM Issue #1604 (Resolved): Unknown node in split color() map on empty if
- Thanks for the good test case.
This was caused by your outputs (rx & ry) never being used, not sure if you noticed... - 08:18 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of the bits that are speci...
- 07:25 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- Wilson Snyder wrote:
> >But it doesn't capture internal behavioral source/destination
>
> It does, for example s...
11/15/2019
- 11:38 PM Issue #1604 (Confirmed): Unknown node in split color() map on empty if
- Will require some research. The irony is the point of the broken optimization is to transform it into exactly what y...
- 10:35 PM Issue #1604 (Closed): Unknown node in split color() map on empty if
- ...
- 11:25 PM Issue #1605 (Resolved): for loop initialisation clause skipped
- Sorry, that's nasty and should have been caught earlier, so fixing immediately.
FWIW "for (i=1; 0; )" was tested, ... - 10:47 PM Issue #1605 (Closed): for loop initialisation clause skipped
- The body of the first for loop in this code never executes because the condition clause is always false; however it s...
- 08:48 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- >But it doesn't capture internal behavioral source/destination
It does, for example see the varref (references to... - 08:41 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- Wilson Snyder wrote:
> Verilog-perl has some of this information, but from what you describe I would suggest first l... - 09:36 AM Issue #1598: Problems attempting to redefine VL_PRINTF
- Thanks for the pointers, I will persevere with that aproach and try and get a patch out ...
- 08:39 AM Issue #1598 (Confirmed): Problems attempting to redefine VL_PRINTF
- Originally VL_PRINTF was intended to be overridden in a .mk file which overrode the default verilator.mk file. For t...
- 09:08 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
- This is to protect against what in some cases may become:
int foo;
void foo();
which causes a mess of course. ... - 02:11 AM Issue #1603: Statement label should be allowed to be a duplicate of a parameter
- Ok well that formatting failed - trying again:
This syntax is not allowed by verilator:... - 02:09 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
- This syntax is not allowed by verilator:...
- 08:02 AM Issue #1595 (Assigned): Fix interface reference tracing
- 08:02 AM Issue #1602 (Assigned): Investigate Travis CMake error message
- 08:01 AM Issue #1601 (Confirmed): Add SystemC to Travis
- Hopefully someone has a pre-built package otherwise we'll need to build it, as too slow/unstable to build every time....
- 07:59 AM Issue #1600 (Confirmed): Add vcddiff to Travis
- 07:59 AM Issue #1600: Add vcddiff to Travis
- Might want to put a binary somewhere as this almost never changes.
11/14/2019
- 11:09 PM Issue #1602 (Assigned): Investigate Travis CMake error message
- I've only seen this in Travis (and maybe only with Trusty). It was showing up in the logs because of a probably unre...
- 11:06 PM Issue #1601 (Confirmed): Add SystemC to Travis
- SystemC tests are being skipped right now.
- 11:05 PM Issue #1600 (Closed): Add vcddiff to Travis
- A number of tests are not running because this is missing.
- 11:04 PM Issue #1596 (Resolved): Travis tweaks
- Squashed and pushed to both repos. I added some Makefile logic to examples/xml_py to skip the example if Python < 3....
- 09:04 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
- Verilog-perl has some of this information, but from what you describe I would suggest first looking at Verilator's --...
- 06:40 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
- I have trying to form a signal connectivity Parser within a Module file. It Can read (one or multiple) Verilog files ...
- 03:27 PM Issue #1598 (Closed): Problems attempting to redefine VL_PRINTF
- I need my verilated model to call something other than printf to perform output $display, and the intended way to do ...
11/13/2019
- 10:56 PM Issue #1596: Travis tweaks
- That example isn't terribly important. I suggest I just only run it if python is new enough, rather than take the 3 ...
- 09:38 PM Issue #1596: Travis tweaks
- The other option here is to install Python 3.5 on the Trusty image. This is the latest version of Python3 that Ubunt...
- 01:28 PM Issue #1596: Travis tweaks
- I think we should aim to allow 14.04, or at least plan to until we find something painful.
Thanks for diagnosing e... - 01:24 PM Issue #1596: Travis tweaks
- Great, I'll keep that in mind. I've gone down a bit of a rabbit hole here and am cleaning up a few more things. One...
- 09:39 PM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- I'm not sure if you mean that the warning can be disabled for my case or the fundamental issue can be fixed for my ca...
- 12:34 AM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- Good point, raised to normal. Perhaps if I provide some pointers you could attempt a patch to the warning (which sho...
- 02:15 PM Issue #1597 (AskedReporter): building verilator from source package
- By setting VERILATOR_ROOT that overrides the default you set for prefix, just don't set that and it should work, let ...
- 01:59 PM Issue #1597 (NoFixNeeded): building verilator from source package
- Dear Community,
I've compiled the Verilator from scratch.
Untar the verilator-4.016.tgz.
cd /home/myhome/myloc...
11/12/2019
- 10:17 PM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- I am running into this problem very frequently with RTL that extensively uses packed structs. For instance this does...
- 11:29 AM Issue #1596: Travis tweaks
- Looks good. Feel free to continue to ask, but also feel free to push any travis or other changes you feel reasonably...
- 10:38 AM Issue #1596 (Closed): Travis tweaks
- See:
https://github.com/toddstrader/verilator-dev/tree/travis-tweaks
and:
https://github.com/toddstrader/verilator...
11/11/2019
- 01:34 PM Issue #1595: Fix interface reference tracing
- The scopes are known once V3Scope completes, so yes they are known.
I'm not sure what the easiest way to know from... - 01:08 PM Issue #1595 (Closed): Fix interface reference tracing
- I discovered that my commit for bug1594 is not yet working (and unfortunately escaped into 4.022). The problem is th...
11/10/2019
- 07:30 PM Issue #1519 (Closed): Benchmark --protect-lib runtime
- In 4.022.
(& thanks for all your work in this release) - 07:29 PM Issue #1581 (Closed): Ranges starting with zero result in unsigned/constant warning
- In 4.022.
- 07:28 PM Issue #1490 (Closed): Add an option to create a DPI protected library
- In 4.022.
- 07:28 PM Issue #1363 (Closed): CMake support
- In 4.022.
- 07:28 PM Issue #1521 (Closed): Add --protect-ids to enhance --protect-lib obfuscation
- In 4.022.
- 07:28 PM Issue #1315 (Closed): Using an array in a function called from a parameter
- In 4.022.
- 12:27 AM Issue #1315: Using an array in a function called from a parameter
- Could you look again at bug1484 and maybe add it to the regression? It doesn't work with the basic support that was c...
- 07:28 PM Issue #1594 (Closed): Add interface port visibility in traces
- In 4.022.
- 07:28 PM Issue #1535 (Closed): Double quotes in -f option file
- In 4.022.
- 07:28 PM Issue #1570 (Closed): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpack ...
- In 4.022.
- 01:43 AM Issue #1484: Parameter of an array of enumeration values breaks conditionals inside a generate block
- Silly mistake :( Thank you for looking at it!
- 01:32 AM Issue #1484: Parameter of an array of enumeration values breaks conditionals inside a generate block
- Note bug1315 is fixed in git, now this example fails with
%Error: t/t_param_array6.v:58: Illegal assignment of ...
11/09/2019
- 11:37 PM Issue #1578: Support unpacked array function constantization
- bug1315 has been fixed in git towards eventual 4.022 release.
This example passes when:
parameter MASK = ma... - 11:33 PM Issue #1315 (Resolved): Using an array in a function called from a parameter
- Basic support for parameter arrays is committed to git towards eventual 4.022 release.
Note the example provided n...
11/08/2019
- 02:02 PM Issue #1594 (Resolved): Add interface port visibility in traces
- Done.
- 12:06 PM Issue #1594 (Assigned): Add interface port visibility in traces
- Good idea.
Only nit is to put braces around the iteration and reorder a bit to clarify how you are save/restoring ... - 11:52 AM Issue #1594 (Closed): Add interface port visibility in traces
- See:
https://github.com/toddstrader/verilator-dev/tree/iface-vcd
Users should not have to know where an interface... - 01:13 PM Issue #1523: Add waveform replay tool
- > I'd suggest instead to look at using the gtkwave libraries.
Good point, I'll check out that codebase too. I'll ... - 03:34 AM Issue #1544 (Closed): Improve readme
- Rewrote readme, install, and updated URLs.
11/07/2019
- 11:43 PM Issue #1523: Add waveform replay tool
- >https://github.com/ben-marshall/verilog-vcd-parser
>Before I go to much further down this path, I wanted to discuss... - 04:21 PM Issue #1523: Add waveform replay tool
- You are correct that this should not be tied to --protect-lib. I've updated the subject accordingly.
I have somet... - 11:17 PM Issue #1593 (Confirmed): Parameter-resolved constants from interface components
- I think it's also a bug that the workaround works, any reference into a child (which an interface is) should have had...
- 04:39 PM Issue #1593: Parameter-resolved constants from interface components
- Yeah, I keep bumping into this one too. Verilator should be able to take $bits() of that signal in the same way that...
- 04:22 PM Issue #1593 (Confirmed): Parameter-resolved constants from interface components
- When doing something like this:
localparam MY_WIDTH = $bits({my_intf.signal1, my_intf.signal2});
We get the follo... - 12:48 AM Issue #1556 (Closed): More informative did not converge message
- Not perfect (still not great line number), but a lot more trail to follow now.
- 12:18 AM Issue #1590: Fuzzer: Segfault on parameter as generate condition
- Perhaps I'm missing some detail, but can't you just tweak actual_fail to not be interesting if there was %Error printed?
11/06/2019
- 11:10 PM Issue #1590: Fuzzer: Segfault on parameter as generate condition
- Regarding only crashes with no output, that's easier said than done. I don't know of any fuzzer capable of doing tha...
- 02:15 AM Issue #1570 (Resolved): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpac...
- Fixed in git towards eventual 4.022 release.
- 12:35 AM Issue #1589: Fuzzer: Segfault on genvar out of scope
- Regarding the scope: that's interesting. I think you're right but it took me longer to confirm that than I expected....
11/05/2019
- 01:51 PM Issue #1580 (Closed): test_regress/t_prot_lib is unstable
- Done.
- 01:43 PM Issue #1580: test_regress/t_prot_lib is unstable
- Thanks, feel free to push and close, no need for a Changes update.
- 12:43 PM Issue #1580: test_regress/t_prot_lib is unstable
- This should resolve the issue and make the tests self-contained:
https://github.com/toddstrader/verilator-dev/tree/p... - 03:10 AM Issue #1554 (AskedReporter): There is a problem when Handling variables forced type conversion
- Waiting on standalone test case.
- 03:10 AM Issue #1555 (NoFixNeeded): Asynchronous reset logic is inconsistent with rtl
- 03:09 AM Issue #1524 (Assigned): Support sensitivity to DPI function outputs
- 03:00 AM Issue #1579 (Closed): Fuzzer: Segfault on initialization from invalid expression
- Fixed in git by adding Internal error.
- 02:51 AM Issue #1586 (Closed): Fuzzer: Segfault on sliced compare with different shapes
- Fixed in git towards 4.022.
- 02:41 AM Issue #1587 (Duplicate): Fuzzer: Segfault with no diagnostic with "--coverage" and different widths
- Same root cause as bug1586.
- 02:21 AM Issue #1588 (Closed): Fuzzer: Segfault on interface index out of range
- Fixed in git and __DOT cleaned up.
- 02:16 AM Issue #1589 (Closed): Fuzzer: Segfault on genvar out of scope
- Generate dosn't make a scope, begin/end does. Basically generate was a Verilog 2001 thing now not needed.
Cleaned... - 12:33 AM Issue #1590 (Closed): Fuzzer: Segfault on parameter as generate condition
- Fixed in git towards 4.022.
- 12:29 AM Issue #1591 (Closed): Fuzzer: Segfault on $left of non-scalar
- Fixed in git towards 4.022.
- 12:11 AM Issue #1583 (Closed): Fuzzer: Segfault on illegal pattern assignment
- Fixed in git towards 4.022.
Basically just added an internal error. As noted elsewhere we probably should focus m... - 12:11 AM Issue #1585 (Closed): Fuzzer: Segfault on illegal port use
- Fixed in git towards 4.022.
Basically just added an internal error. As noted elsewhere we probably should focus m... - 12:05 AM Issue #1584 (Duplicate): Fuzzer: Segfault on pattern assignment
- Same issue as bug1583.
- 12:00 AM Issue #1592 (Confirmed): $value_plusargs compile error for [1..16]-bit signals
- Great, love getting bugs with fixes included!
Two minor things to add to your patch so I can merge it and make sur...
11/04/2019
- 11:51 PM Issue #1582 (Closed): Fuzzer: Out of memory on enum with self value
- Thanks, fixed in git towards 4.022.
- 04:45 PM Issue #1582 (Closed): Fuzzer: Out of memory on enum with self value
- Running the attached testcase with:
verilator_bin --lint-only 2.sv
On version:
Verilator 4.020 devel rev v4.... - 11:26 PM Issue #1592 (Closed): $value_plusargs compile error for [1..16]-bit signals
- Passing signals of length <= 16 bits to $value$plusargs results in compiler errors due to missing overloads for CData...
- 08:27 PM Issue #1591 (Closed): Fuzzer: Segfault on $left of non-scalar
- Running the attached testcase with:
verilator_bin --lint-only 9.sv
On version:
Verilator 4.020 devel rev v4.... - 08:04 PM Issue #1590: Fuzzer: Segfault on parameter as generate condition
- I'll look at this and the others starting tonight.
In the interest of best use of time, I'd recommend we only look... - 07:49 PM Issue #1590 (Closed): Fuzzer: Segfault on parameter as generate condition
- Running the attached testcase with:
verilator_bin --lint-only 8.sv
On version:
Verilator 4.020 devel rev v4.... - 07:32 PM Issue #1589 (Closed): Fuzzer: Segfault on genvar out of scope
- Running the attached testcase with:
verilator_bin --lint-only 7.sv
On version:
Verilator 4.020 devel rev v4.... - 06:54 PM Issue #1588 (Closed): Fuzzer: Segfault on interface index out of range
- Running the attached testcase with:
verilator_bin --lint-only 6.sv
on version:
Verilator 4.020 devel rev v4.... - 06:34 PM Issue #1587 (Duplicate): Fuzzer: Segfault with no diagnostic with "--coverage" and different widths
- Running the attached testcase with:
verilator_bin --lint-only --coverage 5.sv
On version:
Verilator 4.020 de... - 06:15 PM Issue #1586 (Closed): Fuzzer: Segfault on sliced compare with different shapes
- Running the attached testcase with:
verilator_bin --lint-only 4.sv
On version:
Verilator 4.020 devel rev v4.... - 05:47 PM Issue #1584: Fuzzer: Segfault on pattern assignment
- It seems that I missed uploading the testcase here.
- 05:25 PM Issue #1584 (Duplicate): Fuzzer: Segfault on pattern assignment
- Running the attached testcase with:
verilator_bin --lint-only 2.sv
Produces:... - 05:46 PM Issue #1583: Fuzzer: Segfault on illegal pattern assignment
- Much harder to reproduce without the testcase.
- 05:03 PM Issue #1583 (Closed): Fuzzer: Segfault on illegal pattern assignment
- Running the attached testcase with:
verilator_bin --lint-only 1.sv
On version:
Verilator 4.020 devel rev v4.... - 05:45 PM Issue #1585 (Closed): Fuzzer: Segfault on illegal port use
- With the attached testcase, runing:
verilator_bin --lint-only 3.sv
with version:
Verilator 4.020 devel rev v...
11/02/2019
- 08:56 PM Issue #1581 (Resolved): Ranges starting with zero result in unsigned/constant warning
- Thanks for the good report. Verilator internally converts the inside to <= or >=, which normally give those warnings,...
- 06:49 PM Issue #1581: Ranges starting with zero result in unsigned/constant warning
- Note: It also seems to have a range issue issue if the range extends to the end of the range (8'hff). Works if I spl...
- 06:28 PM Issue #1581 (Closed): Ranges starting with zero result in unsigned/constant warning
- Trying to use the inside operator with a range, had multiple functions fail on warnings and realized it was all that ...
- 04:46 PM Issue #1580: test_regress/t_prot_lib is unstable
- Todd wrote it originally...
- 03:24 PM Issue #1580 (Closed): test_regress/t_prot_lib is unstable
- Debugging a test makefile cleanup, I realized why t_prot_lib and t_noprot_lib seem to fail occasionally for me, but t...
- 03:27 PM Issue #1578 (Duplicate): Support unpacked array function constantization
- Thanks for your report. Using arrays in constifications is unsupported at present. There's been some recent work but ...
11/01/2019
- 10:38 PM Issue #1579 (Closed): Fuzzer: Segfault on initialization from invalid expression
- Running the attached testcase with:
verilator_bin --lint-only 1.sv
On version:
Verilator 4.020 devel rev v4....
10/31/2019
- 01:24 PM Issue #1578 (Duplicate): Support unpacked array function constantization
- If I write something like:...
- 01:49 AM Issue #1577 (Closed): Fuzzer: Segfault on undeclared in sensitivity list
- Fixed in git.
10/30/2019
- 11:34 PM Issue #1577 (Closed): Fuzzer: Segfault on undeclared in sensitivity list
- Running the attached testcase with:
verilator_bin --lint-only 2a.sv
On version:
Verilator 4.020 devel rev v4... - 10:19 PM Issue #1576 (Closed): Fuzzer: Missing error when parameter assigned to type "realtime"
- bug1575's fix wasn't quite in the right spot.
Fixed in git.
- 05:06 PM Issue #1576 (Closed): Fuzzer: Missing error when parameter assigned to type "realtime"
- Running the attached testcase with:
verilator_bin --cc --trace 1.sv
with version:
Verilator 4.020 devel rev ...
10/29/2019
- 10:39 PM Issue #1575 (Closed): Fuzzer: Missing error when parameter assigned to type
- Should have thought of that test case earlier, error added.
- 08:21 PM Issue #1575 (Closed): Fuzzer: Missing error when parameter assigned to type
- Running the attached testcase with
verilator_bin --lint-only --trace 1.sv
with version:
Verilator 4.020 dev... - 07:04 PM Issue #1574: Fuzzer: Hang on inifinite define expansion
- I'm glad this one was useful. I don't have a great procedure for figuring out what a minimal testcase looks like for...
- 02:35 AM Issue #1574 (Closed): Fuzzer: Hang on inifinite define expansion
- Good & relevant one. It's basically this...
- 02:46 AM Issue #1547 (Closed): Refactor Verilator building in Travis
10/28/2019
- 11:35 PM Issue #1572 (Feature): Extend --protect-lib for foreign/embedded module use
- 11:34 PM Issue #1573 (Closed): Fuzzer: Segfault after unsupported struct/union
- Fixed in git, thanks for the test.
- 07:53 PM Issue #1573 (Closed): Fuzzer: Segfault after unsupported struct/union
- Running the attached testcase with:
verilator_bin --lint-only 1.sv
With version:
Verilator 4.020 devel rev v... - 08:00 PM Issue #1574 (Closed): Fuzzer: Hang on inifinite define expansion
- Running the attached testcase with:
verilator_bin --lint-only 2.sv
On version:
Verilator 4.020 devel rev v4....
10/25/2019
- 12:11 PM Issue #1522: Support mutable top-level parameters for --protect-lib
- Agreed, I'm not going to dive into anything here before we have a well baked plan.
But in the interest of writing ...
10/24/2019
- 12:21 PM Issue #1572: Extend --protect-lib for foreign/embedded module use
- One more for the list:
* Add parameters from the embedded module in the SV wrapper and (assuming one was built) use ... - 11:50 AM Issue #1572 (Feature): Extend --protect-lib for foreign/embedded module use
- See:
https://www.veripool.org/boards/3/topics/2348
--protect-lib can be used for foreign modules/incremental comp... - 11:33 AM Issue #1535 (Resolved): Double quotes in -f option file
- Great, thanks for the work.
Pushed to git towards eventual 4.022 release.
- 11:17 AM Issue #1535: Double quotes in -f option file
- Wilson Snyder wrote:
> I think good to go (with a few trivial space issues I'll fix). May I use the email you regis... - 11:14 AM Issue #1535: Double quotes in -f option file
- I think good to go (with a few trivial space issues I'll fix). May I use the email you registered under for the git ...
- 10:56 AM Issue #1535: Double quotes in -f option file
- Wilson Snyder wrote:
> Looking good.
>
> 1. You don't check for escaped chars inside single quotes. I might have ...
10/23/2019
- 05:06 PM Issue #1519 (Resolved): Benchmark --protect-lib runtime
- Yeah, sorry. The intent is to push this. I'm sure we'll want to evolve the benchmarking over time, but focusing on ...
- 12:26 PM Issue #1535: Double quotes in -f option file
- Looking good.
1. You don't check for escaped chars inside single quotes. I might have missed it but didn't see tha... - 07:18 AM Issue #1535: Double quotes in -f option file
- New proposal updated taking into account your last post.
* fixed style, upercase, ...
* removed parsing of '='
*...
10/22/2019
- 10:26 PM Issue #1519: Benchmark --protect-lib runtime
- Not sure if you are proposing to merge this...
1. Some tabs got into t_prot*, please squash them.
2. You should... - 10:01 PM Issue #1519: Benchmark --protect-lib runtime
- See:
https://github.com/toddstrader/verilator-dev/tree/prot-lib-benchmark
This adds t_noprot_lib which is the sam...
10/20/2019
- 06:52 PM Issue #1571 (NoFixNeeded): Memory definition triggers the error "Signal unoptimizable: Feedback t...
- The problem isn't that line per-se, but rather the places where it's used. In the case you provided this is a behavi...
- 06:37 PM Issue #1571: Memory definition triggers the error "Signal unoptimizable: Feedback to clock or cir...
- Here they declare the memory in essentially the same way: http://www.asic-world.com/verilog/memory_fsm1.html
- 06:34 PM Issue #1571 (NoFixNeeded): Memory definition triggers the error "Signal unoptimizable: Feedback t...
- I have this statement defining the memory that triggers this error:...
- 01:21 PM Issue #1570 (Confirmed): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpa...
- Yes, it should warn, will look into it.
- 12:06 PM Issue #1570: Verilog 2001: verilator does not issue a warning on missing 'reg', Webpack ISE 14.7 ...
- I am sorry for the Webpack layout, this is the first time. And I also do not know how to fix it.
The verilator co... - 12:04 PM Issue #1570 (Closed): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpack ...
- I used the most recent master commit of verilator to show this problem exists in the current master branch.
Take t... - 12:00 PM Issue #1569 (WillNotFix): $monitor statement isn't supported
- Thanks for your report.
At this time Verilator doesn't have a time wheel, so doesn't really have a way to properly... - 08:59 AM Issue #1569 (WillNotFix): $monitor statement isn't supported
- Here the $monitor statement is described: http://www.referencedesigner.com/tutorials/verilog/verilog_09.php
Here is ...
10/19/2019
- 12:23 PM Issue #1489: Python support for Verilated designs
- Review comments:
+++ b/bin/verilator
+=item --python
+
+This generates a file wraps the toplevel mo... - 11:09 AM Issue #1568 (Closed): Spelling mistakes fixes
- Thanks, pushed along with a few other fixes.
Note you need only change bin/verilator as the HTML/tex/pdf is auto-g... - 05:58 AM Issue #1568 (Closed): Spelling mistakes fixes
- The attached patch fix some spelling mistakes in verilator
- 01:31 AM Issue #1563 (Closed): Fuzzer: Unterminated block comment gives flex scanner internal error--end o...
- Thanks for the test, some user would have hit this too, likely. Fixed in git.
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