Activity
From 10/31/2019 to 11/29/2019
11/27/2019
- 06:25 AM Usage: RE: Trouble simulating altera-generated floating point units
- It's a fundamental problem, try rewriting.
- 02:31 AM Usage: RE: Trouble simulating altera-generated floating point units
- Is this problem fundamentally due to verilator being a cycle simulator instead of an event simulator? Will it be poss...
11/24/2019
- 07:32 PM Usage: RE: Trouble simulating altera-generated floating point units
- Hmm, I don't think it's related to that. I just used 'x' as a variable name in my previous code example. There is alr...
- 01:40 PM Usage: RE: Trouble simulating altera-generated floating point units
- You could try the --x-initial-edge flag. Or, add an initial statement.
- 08:35 AM Usage: RE: Trouble simulating altera-generated floating point units
- Ok, I have figured out the issue, but I am unsure how to solve it. Inside the altera memory sim libraries, there is c...
11/23/2019
- 01:29 AM Usage: RE: Any chance to use Verilator together with Icuras?
- Great! There's been a lot of progress in the last month or so, with --protect-lib added etc, please see bug1572. I'...
- 12:44 AM Usage: RE: Any chance to use Verilator together with Icuras?
- ... "Verilator has plans to add "embedding" of a model in another simulator"
This is exactly how I use Verilator w...
11/22/2019
- 11:21 AM Usage: RE: Trouble simulating altera-generated floating point units
- Glad you're giving Verilator a try. It's most likely something simple, perhaps with a hint buried in a warning as yo...
- It is my first time using verilator. I wrote a simple program to test the floating point units generated by altera's ...
11/19/2019
- 03:06 AM Usage: RE: Basic questions: Multiple modules and using "#"
- 1) Yes, you can put multiple modules per file.
2) You'd write this in C code, for example in = 0; then make time p...
11/18/2019
- Hello,
I want to play with some simple modules and signals and tried this:...
11/13/2019
- 09:52 AM Usage: RE: Very basic eval() usage question
- No idea, obviously makes no sense at first glance; try stepping through in the debugger. Let us know what it turns o...
- I want to write some functions in the same C++ file as the main() function is in which will also call top->eval();
...
11/02/2019
- 11:58 AM Usage: RE: Testbench patterns to run N cycles ?
- It finishes when there's a $finish, that's not really a signal.
Anyhow the example you point to should have s $fin... - Hello,
as I understand from the example sim_main.cc replaces the testbench.
The main loop stops when it receives ... - 10:00 AM Installation: RE: Windows MinGW/Msys based build
- Thanks, yes that works:
pacman -S mingw-w64-x86_64-verilator
Also, thanks for the additional pointers. - 12:11 AM Installation: RE: Windows MinGW/Msys based build
- As I said before, you shouldn't put /usr/include on the path, it will break everything. The easy thing to do is just ...
11/01/2019
- 09:08 PM Installation: RE: Windows MinGW/Msys based build
- In config.log there is already this:...
- 09:03 PM Installation: RE: Windows MinGW/Msys based build
- I tried:
export CPPFLAGS=-I/usr/include...
10/31/2019
- 11:26 AM Development: RE: Anywhere to find the description of cycle based simulator
- Verilator figures out the logic graph of the code, basically as a cone, and starts from inputs evaluating what that n...
- 06:49 AM Development: RE: Anywhere to find the description of cycle based simulator
- Or simply evaluate twice without advance the time?
- 05:48 AM Development: RE: Anywhere to find the description of cycle based simulator
- Thanks Wilson.
The general understand of the CBS algorithm is:
1. simulate all combinational elements;
2. s...
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