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Activity

From 11/03/2019 to 12/02/2019

12/02/2019

09:19 PM Issue #1595: Fix interface reference tracing
Latest updates are still in this branch:
https://github.com/toddstrader/verilator-dev/tree/iface-trace-perf
I am ...
Todd Strader
02:07 PM Issue #1618: Travis Mail not going to authors?
If travis has nothing to fix this, perhaps instead of overriding email, have a end-of-run script that simply does a s... Wilson Snyder
01:16 PM Issue #1618 (Confirmed): Travis Mail not going to authors?
You're right. The default Travis behavior is to email the author and committer. But if you specify an email recipie... Todd Strader
12:58 PM Issue #1618 (Closed): Travis Mail not going to authors?
Re issue 1617:
BTW, something, maybe your email-yourself?, seems to have broken the author of the commit getting e...
Wilson Snyder
01:35 PM Issue #1616 (Closed): Intenal Error of "Multiple root modules" happens if one of sub modules is n...
Fixed in git towards 4.024. Todd Strader
12:59 PM Issue #1617 (Closed): Assoc array adds C++11 in the codebase
Passed in travis, thanks for the report.
Filed bug1618 for travis "BTW" above.
Wilson Snyder
11:19 AM Issue #1617 (Confirmed): Assoc array adds C++11 in the codebase
Sorry, that include slipped through I had added a new class instead of using array and forgot to remove the include. ... Wilson Snyder
11:01 AM Issue #1617 (Closed): Assoc array adds C++11 in the codebase
The associative arrays commit has broken Travis:
https://github.com/verilator/verilator/commit/b81295230a866e38c4183...
Todd Strader

12/01/2019

10:20 PM Issue #1614 (Resolved): Multiple label redefinition/parsing issue for constant functions used in ...
Fixed in git towards eventual 4.024 release.
Wilson Snyder
05:43 PM Issue #1615 (Closed): --output-split units documented as bytes, but appears to be closer to lines
Fixed in git.
Wilson Snyder
05:36 PM Issue #545 (Resolved): Support queues
Initial queue support (using method notation, not {} notation) is in git towards eventual 4.024 release.
Wilson Snyder
04:54 PM Issue #544 (Resolved): Support associative arrays
Associative array support for general types, excluding [*] and pattern assignment, is in git for eventual 4.024 relea... Wilson Snyder
04:01 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
Sorry, missed that, looks fine.
Wilson Snyder
01:02 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
m_foundTop is already in the constructor initializer list. Is it fine there or should I move it to the constructor's... Todd Strader
10:58 AM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
Todd, thanks for fixing. Feel free to push, you just need to init m_foundTop = false in the constructor.
Wilson Snyder

11/30/2019

04:37 PM Issue #1616 (Confirmed): Intenal Error of "Multiple root modules" happens if one of sub modules i...
That check was overly aggressive when inlining. Here's my proposed solution:
https://github.com/toddstrader/verilat...
Todd Strader

11/29/2019

11:21 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
Thanks for the example. I'll take a look. Todd Strader
10:43 PM Issue #1616 (Closed): Intenal Error of "Multiple root modules" happens if one of sub modules is n...
First of all, thank you very much for maintaining and evolving the great software.
I am exploring --protect-lib to...
Yutetsu TAKATSUKASA
08:13 PM Issue #1595: Fix interface reference tracing
Yeah, I'll just need some C str functions in the generated code to concatenate the two parts of the name. I'll do th... Todd Strader
07:20 PM Issue #1595: Fix interface reference tracing
I don't understand the need to change the include/ headers. I would think calling these decl functions with the prope... Wilson Snyder
05:14 PM Issue #1595: Fix interface reference tracing
What I've ended up on is creating a new AstIntfRef which is a child of AstCell nodes which are interfaces. These alw... Todd Strader

11/27/2019

02:07 PM Issue #1369: Raise error / warning on continous assignment to reg
Warning about assigning to output reg does not work for me. I'm using tag 4.022 without success.... Peter Gerst
11:12 AM Issue #1615 (Confirmed): --output-split units documented as bytes, but appears to be closer to lines
Thanks, will update these in the docs.
Output-split is roughly number of statements.
Wilson Snyder
10:58 AM Issue #1615: --output-split units documented as bytes, but appears to be closer to lines
It would also be worth mentioning that VM_PARALLEL_BUILDS needs to be set to 1 on the make command line to exploit pa... Julien Margetts
10:29 AM Issue #1615 (Closed): --output-split units documented as bytes, but appears to be closer to lines
The manual states the units of the --output-split option as bytes in both the summary and the full description, but i... Julien Margetts

11/26/2019

06:44 PM Issue #1614 (Confirmed): Multiple label redefinition/parsing issue for constant functions used in...
Will take a look.
You might also be able to work around it by replacing the return with "min=..."
Wilson Snyder

11/25/2019

03:24 PM Issue #1614 (Closed): Multiple label redefinition/parsing issue for constant functions used in co...
Minimal case below... Mitch Hayenga

11/23/2019

01:31 AM Issue #1572: Extend --protect-lib for foreign/embedded module use
For those looking to try embedding without protection, for just for experimentation, use a recent git version and try... Wilson Snyder

11/22/2019

11:13 PM Issue #1613 (Confirmed): verilator %Warning-WIDTH false positive
You're right, an easy cross check:
$display("%d", $size(o_dec_table.dec_len));
16
What looks to be...
Wilson Snyder
08:35 PM Issue #1613: verilator %Warning-WIDTH false positive
I think what I said above is consistent with IEEE 1800-2017 7.4.5 which says (among other things), "A subarray is an ... Tim Allen
07:44 PM Issue #1613: verilator %Warning-WIDTH false positive
does ... Tim Allen
05:21 PM Issue #1613: verilator %Warning-WIDTH false positive
The rightmost index of dec_len is 31:0, meaning it needs 6 bits to index into. Your cur_bit_len as you indicate is on... Wilson Snyder
03:28 PM Issue #1613 (Confirmed): verilator %Warning-WIDTH false positive
excerpt of file.sv...... Tim Allen
08:35 PM Issue #1612 (Closed): New VPI tests failing clang and Trusty builds
Cron seems happy now:
https://travis-ci.com/verilator/verilator/builds/137738748
Todd Strader

11/21/2019

11:43 PM Issue #1612 (Confirmed): New VPI tests failing clang and Trusty builds
Fixed, had uninit variable. Leaving open for now to see if Travis is happy.
Also added an error when test core du...
Wilson Snyder
12:57 PM Issue #1612 (Closed): New VPI tests failing clang and Trusty builds
Appears similar to bug1611. See:
https://travis-ci.com/verilator/verilator/builds/137544069
Affects --vlt and --...
Todd Strader

11/20/2019

11:49 PM Issue #1609 (Feature): Detect and warn appripriately on intentional latches
Wilson Snyder
11:48 PM Issue #1609 (Assigned): Detect and warn appripriately on intentional latches
Great, would be awesome to get this in.
The sensitivity list will at that point have some elements with combo on i...
Wilson Snyder
01:57 PM Issue #1609: Detect and warn appripriately on intentional latches
To ignore intentional standalone latches I think I need to update class ActiveDlyVisitor to supress the warning if th... Julien Margetts
03:36 AM Issue #1609: Detect and warn appripriately on intentional latches
Not sure I'm interpreting the question correctly, but...
Verilator doesn't presently identify self-identify latche...
Wilson Snyder
11:58 AM Issue #1611 (Closed): New VPI tests failing under --vltmt
Thanks, worked for me as builds went in different order, but should have noticed that code.
Fix pushed.
Wilson Snyder
10:40 AM Issue #1611 (Closed): New VPI tests failing under --vltmt
Two tests from this PR are failing CI under --vltmt:
https://github.com/verilator/verilator/pull/5
See:
https://...
Todd Strader
03:21 AM Issue #1595: Fix interface reference tracing
You can't have cells point to varscopes as it's a many-to-one arrangement, which is why scopes exist in the first pla... Wilson Snyder
12:24 AM Issue #1608 (Resolved): Strange dotted expression makes Verilator hang, but print correct error m...
Thanks for the report.
Fixed in git towards eventual 4.024 release.
Wilson Snyder

11/19/2019

03:30 PM Issue #1609 (Feature): Detect and warn appripriately on intentional latches
According to Cummings:
"Guideline #2: When modeling latches, use nonblocking assignments."
However, as I'm sure y...
Julien Margetts
12:39 PM Issue #1595: Fix interface reference tracing
I'm now thinking that the cleaner way to do this is to TraceDecl the entire interface. That way we can emit a TraceD... Todd Strader
10:37 AM Issue #1608 (Closed): Strange dotted expression makes Verilator hang, but print correct error mes...
The following module makes Verilator hang... Bogdan Vukobratovic
03:11 AM Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
Wilson Snyder

11/18/2019

10:04 AM Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
A pull is out against GTKwave. Once this completes:
- Move personal script to compare GTKwave include upstream to ...
Wilson Snyder

11/17/2019

06:39 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of...
Aimless Ramble
11:42 AM Issue #1605: for loop initialisation clause skipped
Thanks for fixing it so quickly. Andrew Holme
11:36 AM Issue #1604: Unknown node in split color() map on empty if
Thanks for fixing it. I had not attached any significance to them being unused; however, there are three instances o... Andrew Holme
09:58 AM Issue #1606 (Resolved): Complete string methods (starter project)
Implement the built-in string methods that are remaining:
- atobin, atohex, atoi, atooct, atoreal: Become a scanf....
Wilson Snyder

11/16/2019

10:24 PM Issue #1604 (Resolved): Unknown node in split color() map on empty if
Thanks for the good test case.
This was caused by your outputs (rx & ry) never being used, not sure if you noticed...
Wilson Snyder
08:18 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of the bits that are speci... Wilson Snyder
07:25 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> >But it doesn't capture internal behavioral source/destination
>
> It does, for example s...
Aimless Ramble

11/15/2019

11:38 PM Issue #1604 (Confirmed): Unknown node in split color() map on empty if
Will require some research. The irony is the point of the broken optimization is to transform it into exactly what y... Wilson Snyder
10:35 PM Issue #1604 (Closed): Unknown node in split color() map on empty if
... Andrew Holme
11:25 PM Issue #1605 (Resolved): for loop initialisation clause skipped
Sorry, that's nasty and should have been caught earlier, so fixing immediately.
FWIW "for (i=1; 0; )" was tested, ...
Wilson Snyder
10:47 PM Issue #1605 (Closed): for loop initialisation clause skipped
The body of the first for loop in this code never executes because the condition clause is always false; however it s... Andrew Holme
08:48 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
>But it doesn't capture internal behavioral source/destination
It does, for example see the varref (references to...
Wilson Snyder
08:41 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> Verilog-perl has some of this information, but from what you describe I would suggest first l...
Aimless Ramble
09:36 AM Issue #1598: Problems attempting to redefine VL_PRINTF
Thanks for the pointers, I will persevere with that aproach and try and get a patch out ... Julien Margetts
08:39 AM Issue #1598 (Confirmed): Problems attempting to redefine VL_PRINTF
Originally VL_PRINTF was intended to be overridden in a .mk file which overrode the default verilator.mk file. For t... Wilson Snyder
09:08 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
This is to protect against what in some cases may become:
int foo;
void foo();
which causes a mess of course. ...
Wilson Snyder
02:11 AM Issue #1603: Statement label should be allowed to be a duplicate of a parameter
Ok well that formatting failed - trying again:
This syntax is not allowed by verilator:...
Pieter Kapsenberg
02:09 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
This syntax is not allowed by verilator:... Pieter Kapsenberg
08:02 AM Issue #1595 (Assigned): Fix interface reference tracing
Wilson Snyder
08:02 AM Issue #1602 (Assigned): Investigate Travis CMake error message
Wilson Snyder
08:01 AM Issue #1601 (Confirmed): Add SystemC to Travis
Hopefully someone has a pre-built package otherwise we'll need to build it, as too slow/unstable to build every time.... Wilson Snyder
07:59 AM Issue #1600 (Confirmed): Add vcddiff to Travis
Wilson Snyder
07:59 AM Issue #1600: Add vcddiff to Travis
Might want to put a binary somewhere as this almost never changes.
Wilson Snyder

11/14/2019

11:09 PM Issue #1602 (Assigned): Investigate Travis CMake error message
I've only seen this in Travis (and maybe only with Trusty). It was showing up in the logs because of a probably unre... Todd Strader
11:06 PM Issue #1601 (Confirmed): Add SystemC to Travis
SystemC tests are being skipped right now. Todd Strader
11:05 PM Issue #1600 (Closed): Add vcddiff to Travis
A number of tests are not running because this is missing. Todd Strader
11:04 PM Issue #1596 (Resolved): Travis tweaks
Squashed and pushed to both repos. I added some Makefile logic to examples/xml_py to skip the example if Python < 3.... Todd Strader
09:04 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
Verilog-perl has some of this information, but from what you describe I would suggest first looking at Verilator's --... Wilson Snyder
06:40 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
I have trying to form a signal connectivity Parser within a Module file. It Can read (one or multiple) Verilog files ... Aimless Ramble
03:27 PM Issue #1598 (Closed): Problems attempting to redefine VL_PRINTF
I need my verilated model to call something other than printf to perform output $display, and the intended way to do ... Julien Margetts

11/13/2019

10:56 PM Issue #1596: Travis tweaks
That example isn't terribly important. I suggest I just only run it if python is new enough, rather than take the 3 ... Wilson Snyder
09:38 PM Issue #1596: Travis tweaks
The other option here is to install Python 3.5 on the Trusty image. This is the latest version of Python3 that Ubunt... Todd Strader
01:28 PM Issue #1596: Travis tweaks
I think we should aim to allow 14.04, or at least plan to until we find something painful.
Thanks for diagnosing e...
Wilson Snyder
01:24 PM Issue #1596: Travis tweaks
Great, I'll keep that in mind. I've gone down a bit of a rabbit hole here and am cleaning up a few more things. One... Todd Strader
09:39 PM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
I'm not sure if you mean that the warning can be disabled for my case or the fundamental issue can be fixed for my ca... Paul Donahue
12:34 AM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
Good point, raised to normal. Perhaps if I provide some pointers you could attempt a patch to the warning (which sho... Wilson Snyder
02:15 PM Issue #1597 (AskedReporter): building verilator from source package
By setting VERILATOR_ROOT that overrides the default you set for prefix, just don't set that and it should work, let ... Wilson Snyder
01:59 PM Issue #1597 (NoFixNeeded): building verilator from source package
Dear Community,
I've compiled the Verilator from scratch.
Untar the verilator-4.016.tgz.
cd /home/myhome/myloc...
thomas arndt

11/12/2019

10:17 PM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
I am running into this problem very frequently with RTL that extensively uses packed structs. For instance this does... Paul Donahue
11:29 AM Issue #1596: Travis tweaks
Looks good. Feel free to continue to ask, but also feel free to push any travis or other changes you feel reasonably... Wilson Snyder
10:38 AM Issue #1596 (Closed): Travis tweaks
See:
https://github.com/toddstrader/verilator-dev/tree/travis-tweaks
and:
https://github.com/toddstrader/verilator...
Todd Strader

11/11/2019

01:34 PM Issue #1595: Fix interface reference tracing
The scopes are known once V3Scope completes, so yes they are known.
I'm not sure what the easiest way to know from...
Wilson Snyder
01:08 PM Issue #1595 (Closed): Fix interface reference tracing
I discovered that my commit for bug1594 is not yet working (and unfortunately escaped into 4.022). The problem is th... Todd Strader

11/10/2019

07:30 PM Issue #1519 (Closed): Benchmark --protect-lib runtime
In 4.022.
(& thanks for all your work in this release)
Wilson Snyder
07:29 PM Issue #1581 (Closed): Ranges starting with zero result in unsigned/constant warning
In 4.022.
Wilson Snyder
07:28 PM Issue #1490 (Closed): Add an option to create a DPI protected library
In 4.022.
Wilson Snyder
07:28 PM Issue #1363 (Closed): CMake support
In 4.022.
Wilson Snyder
07:28 PM Issue #1521 (Closed): Add --protect-ids to enhance --protect-lib obfuscation
In 4.022.
Wilson Snyder
07:28 PM Issue #1315 (Closed): Using an array in a function called from a parameter
In 4.022.
Wilson Snyder
12:27 AM Issue #1315: Using an array in a function called from a parameter
Could you look again at bug1484 and maybe add it to the regression? It doesn't work with the basic support that was c... John Martin
07:28 PM Issue #1594 (Closed): Add interface port visibility in traces
In 4.022.
Wilson Snyder
07:28 PM Issue #1535 (Closed): Double quotes in -f option file
In 4.022.
Wilson Snyder
07:28 PM Issue #1570 (Closed): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpack ...
In 4.022.
Wilson Snyder
07:27 PM Verilator 4.022 Released
Verilator 4.022 2019-11-10
** Add --protect-lib, bug1490. [Todd Strader]
** Add cmake support, bug1363. [...
Wilson Snyder
01:43 AM Issue #1484: Parameter of an array of enumeration values breaks conditionals inside a generate block
Silly mistake :( Thank you for looking at it! John Martin
01:32 AM Issue #1484: Parameter of an array of enumeration values breaks conditionals inside a generate block
Note bug1315 is fixed in git, now this example fails with
%Error: t/t_param_array6.v:58: Illegal assignment of ...
Wilson Snyder

11/09/2019

11:37 PM Issue #1578: Support unpacked array function constantization
bug1315 has been fixed in git towards eventual 4.022 release.
This example passes when:
parameter MASK = ma...
Wilson Snyder
11:33 PM Issue #1315 (Resolved): Using an array in a function called from a parameter
Basic support for parameter arrays is committed to git towards eventual 4.022 release.
Note the example provided n...
Wilson Snyder

11/08/2019

02:02 PM Issue #1594 (Resolved): Add interface port visibility in traces
Done. Todd Strader
12:06 PM Issue #1594 (Assigned): Add interface port visibility in traces
Good idea.
Only nit is to put braces around the iteration and reorder a bit to clarify how you are save/restoring ...
Wilson Snyder
11:52 AM Issue #1594 (Closed): Add interface port visibility in traces
See:
https://github.com/toddstrader/verilator-dev/tree/iface-vcd
Users should not have to know where an interface...
Todd Strader
01:13 PM Issue #1523: Add waveform replay tool
> I'd suggest instead to look at using the gtkwave libraries.
Good point, I'll check out that codebase too. I'll ...
Todd Strader
03:34 AM Issue #1544 (Closed): Improve readme
Rewrote readme, install, and updated URLs.
Wilson Snyder

11/07/2019

11:43 PM Issue #1523: Add waveform replay tool
>https://github.com/ben-marshall/verilog-vcd-parser
>Before I go to much further down this path, I wanted to discuss...
Wilson Snyder
04:21 PM Issue #1523: Add waveform replay tool
You are correct that this should not be tied to --protect-lib. I've updated the subject accordingly.
I have somet...
Todd Strader
11:17 PM Issue #1593 (Confirmed): Parameter-resolved constants from interface components
I think it's also a bug that the workaround works, any reference into a child (which an interface is) should have had... Wilson Snyder
04:39 PM Issue #1593: Parameter-resolved constants from interface components
Yeah, I keep bumping into this one too. Verilator should be able to take $bits() of that signal in the same way that... Todd Strader
04:22 PM Issue #1593 (Confirmed): Parameter-resolved constants from interface components
When doing something like this:
localparam MY_WIDTH = $bits({my_intf.signal1, my_intf.signal2});
We get the follo...
Ahmed Qureshi
12:48 AM Issue #1556 (Closed): More informative did not converge message
Not perfect (still not great line number), but a lot more trail to follow now.
Wilson Snyder
12:18 AM Issue #1590: Fuzzer: Segfault on parameter as generate condition
Perhaps I'm missing some detail, but can't you just tweak actual_fail to not be interesting if there was %Error printed? Wilson Snyder

11/06/2019

11:10 PM Issue #1590: Fuzzer: Segfault on parameter as generate condition
Regarding only crashes with no output, that's easier said than done. I don't know of any fuzzer capable of doing tha... Eric Rippey
02:15 AM Issue #1570 (Resolved): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpac...
Fixed in git towards eventual 4.022 release.
Wilson Snyder
12:35 AM Issue #1589: Fuzzer: Segfault on genvar out of scope
Regarding the scope: that's interesting. I think you're right but it took me longer to confirm that than I expected.... Eric Rippey

11/05/2019

01:51 PM Issue #1580 (Closed): test_regress/t_prot_lib is unstable
Done. Todd Strader
01:43 PM Issue #1580: test_regress/t_prot_lib is unstable
Thanks, feel free to push and close, no need for a Changes update.
Wilson Snyder
12:43 PM Issue #1580: test_regress/t_prot_lib is unstable
This should resolve the issue and make the tests self-contained:
https://github.com/toddstrader/verilator-dev/tree/p...
Todd Strader
03:10 AM Issue #1554 (AskedReporter): There is a problem when Handling variables forced type conversion
Waiting on standalone test case.
Wilson Snyder
03:10 AM Issue #1555 (NoFixNeeded): Asynchronous reset logic is inconsistent with rtl
Wilson Snyder
03:09 AM Issue #1524 (Assigned): Support sensitivity to DPI function outputs
Wilson Snyder
03:00 AM Issue #1579 (Closed): Fuzzer: Segfault on initialization from invalid expression
Fixed in git by adding Internal error.
Wilson Snyder
02:51 AM Issue #1586 (Closed): Fuzzer: Segfault on sliced compare with different shapes
Fixed in git towards 4.022.
Wilson Snyder
02:41 AM Issue #1587 (Duplicate): Fuzzer: Segfault with no diagnostic with "--coverage" and different widths
Same root cause as bug1586.
Wilson Snyder
02:21 AM Issue #1588 (Closed): Fuzzer: Segfault on interface index out of range
Fixed in git and __DOT cleaned up.
Wilson Snyder
02:16 AM Issue #1589 (Closed): Fuzzer: Segfault on genvar out of scope
Generate dosn't make a scope, begin/end does. Basically generate was a Verilog 2001 thing now not needed.
Cleaned...
Wilson Snyder
12:33 AM Issue #1590 (Closed): Fuzzer: Segfault on parameter as generate condition
Fixed in git towards 4.022.
Wilson Snyder
12:29 AM Issue #1591 (Closed): Fuzzer: Segfault on $left of non-scalar
Fixed in git towards 4.022.
Wilson Snyder
12:11 AM Issue #1583 (Closed): Fuzzer: Segfault on illegal pattern assignment
Fixed in git towards 4.022.
Basically just added an internal error. As noted elsewhere we probably should focus m...
Wilson Snyder
12:11 AM Issue #1585 (Closed): Fuzzer: Segfault on illegal port use
Fixed in git towards 4.022.
Basically just added an internal error. As noted elsewhere we probably should focus m...
Wilson Snyder
12:05 AM Issue #1584 (Duplicate): Fuzzer: Segfault on pattern assignment
Same issue as bug1583. Wilson Snyder
12:00 AM Issue #1592 (Confirmed): $value_plusargs compile error for [1..16]-bit signals
Great, love getting bugs with fixes included!
Two minor things to add to your patch so I can merge it and make sur...
Wilson Snyder

11/04/2019

11:51 PM Issue #1582 (Closed): Fuzzer: Out of memory on enum with self value
Thanks, fixed in git towards 4.022.
Wilson Snyder
04:45 PM Issue #1582 (Closed): Fuzzer: Out of memory on enum with self value
Running the attached testcase with:
verilator_bin --lint-only 2.sv
On version:
Verilator 4.020 devel rev v4....
Eric Rippey
11:26 PM Issue #1592 (Closed): $value_plusargs compile error for [1..16]-bit signals
Passing signals of length <= 16 bits to $value$plusargs results in compiler errors due to missing overloads for CData... Garrett Smith
08:27 PM Issue #1591 (Closed): Fuzzer: Segfault on $left of non-scalar
Running the attached testcase with:
verilator_bin --lint-only 9.sv
On version:
Verilator 4.020 devel rev v4....
Eric Rippey
08:04 PM Issue #1590: Fuzzer: Segfault on parameter as generate condition
I'll look at this and the others starting tonight.
In the interest of best use of time, I'd recommend we only look...
Wilson Snyder
07:49 PM Issue #1590 (Closed): Fuzzer: Segfault on parameter as generate condition
Running the attached testcase with:
verilator_bin --lint-only 8.sv
On version:
Verilator 4.020 devel rev v4....
Eric Rippey
07:32 PM Issue #1589 (Closed): Fuzzer: Segfault on genvar out of scope
Running the attached testcase with:
verilator_bin --lint-only 7.sv
On version:
Verilator 4.020 devel rev v4....
Eric Rippey
06:54 PM Issue #1588 (Closed): Fuzzer: Segfault on interface index out of range
Running the attached testcase with:
verilator_bin --lint-only 6.sv
on version:
Verilator 4.020 devel rev v4....
Eric Rippey
06:34 PM Issue #1587 (Duplicate): Fuzzer: Segfault with no diagnostic with "--coverage" and different widths
Running the attached testcase with:
verilator_bin --lint-only --coverage 5.sv
On version:
Verilator 4.020 de...
Eric Rippey
06:15 PM Issue #1586 (Closed): Fuzzer: Segfault on sliced compare with different shapes
Running the attached testcase with:
verilator_bin --lint-only 4.sv
On version:
Verilator 4.020 devel rev v4....
Eric Rippey
05:47 PM Issue #1584: Fuzzer: Segfault on pattern assignment
It seems that I missed uploading the testcase here. Eric Rippey
05:25 PM Issue #1584 (Duplicate): Fuzzer: Segfault on pattern assignment
Running the attached testcase with:
verilator_bin --lint-only 2.sv
Produces:...
Eric Rippey
05:46 PM Issue #1583: Fuzzer: Segfault on illegal pattern assignment
Much harder to reproduce without the testcase. Eric Rippey
05:03 PM Issue #1583 (Closed): Fuzzer: Segfault on illegal pattern assignment
Running the attached testcase with:
verilator_bin --lint-only 1.sv
On version:
Verilator 4.020 devel rev v4....
Eric Rippey
05:45 PM Issue #1585 (Closed): Fuzzer: Segfault on illegal port use
With the attached testcase, runing:
verilator_bin --lint-only 3.sv
with version:
Verilator 4.020 devel rev v...
Eric Rippey
 

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