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Activity
From 11/10/2019 to 12/09/2019
12/09/2019
- 06:55 PM Issue #1590: Fuzzer: Segfault on parameter as generate condition
- Yes, that change can be made. Unfortunately though, this makes it unlikely to find anything. The fuzzer itself tend...
- 06:13 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
- VCS and NCSIM behave the same. I do not have access to Modelsim and it does not appear to be an option on edaplaygrou...
- 05:33 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
- LITENDIAN was intended not to change the results.
Can you please run this on all of the big-3 e.g. on edaplaygroun... - 03:14 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
- A brief scan of the LRM has left me still unsure of what the correct behaviour should be
- 03:12 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
- Actually, the difference between VCS and Verilator is that when connecting the elements of the +array+ 'cval' to the ...
- 01:55 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
- Changing only the declaration of inc from an N-bit LE vector, to a an N element LE array, makes the output match, and...
- 01:33 PM Issue #1631 (Resolved): -Wno-lint disables LITENDIAN and allows silent generation of code inconsi...
- The manual states "Ranges must be big-bit-endian" so I think LITENDIAN should not be a member of lintError() and shou...
- 05:40 PM Issue #1606: Complete string methods (starter project)
- I'm sorry, I misread the added includes as being in the .h file. Adding includes is fine in the verilated.cpp file.
... - 02:39 PM Issue #1606: Complete string methods (starter project)
- Thanks again for the comments.
I have updated the branch other than the following item.
> Adding these will slow ... - 09:44 AM Issue #1630: Not able to force values on wires in positive edge of clock cycle
- I ran verilator with the following commands:
verilator -Wall --cc --trace counter.v --exe tb_counter.cpp
make -... - 09:40 AM Issue #1630 (NoFixNeeded): Not able to force values on wires in positive edge of clock cycle
- For a simple counter module, i was trying to force some wires from the test bench.
I declared the wires as public in... - 02:55 AM Issue #1629 (WillNotFix): Optimize wide vectors to use 64 bit entries
- This is to capture notes on a performance experiment.
Verilator uses arrays of 32-bit words for signals over 64 bi...
12/08/2019
- 01:13 PM Issue #1596 (Closed): Travis tweaks
- In 4.024.
- 01:13 PM Issue #1604 (Closed): Unknown node in split color() map on empty if
- In 4.024.
- 01:12 PM Issue #1605 (Closed): for loop initialisation clause skipped
- In 4.024.
For additional support related to this please file new bug.
- 01:12 PM Issue #1608 (Closed): Strange dotted expression makes Verilator hang, but print correct error mes...
- In 4.024.
For additional support related to this please file new bug.
- 01:12 PM Issue #544 (Closed): Support associative arrays
- In 4.024.
For additional support related to this please file new bug.
- 01:12 PM Issue #545 (Closed): Support queues
- In 4.024.
For additional support related to this please file new bug.
- 01:11 PM Issue #1614 (Closed): Multiple label redefinition/parsing issue for constant functions used in co...
- In 4.024.
- 01:11 PM Issue #1592 (Closed): $value_plusargs compile error for [1..16]-bit signals
- In 4.024.
- 01:11 PM Issue #1619 (Closed): $value$plusargs compile error for real types (%e / %f / %g unsupported)
- In 4.024.
- 01:11 PM Issue #1620 (Closed): Dotted function reference causes Internal Error
- In 4.024.
- 01:11 PM Issue #1595 (Closed): Fix interface reference tracing
- In 4.024.
- 01:11 PM Issue #831 (Closed): Gate optimizer: Can't replace lvalue assignments with const var
- In 4.024.
- 01:10 PM Verilator 4.024 Released
- Verilator 4.024 2019-12-08
** Support associative arrays (excluding [*] and pattern assignments), bug544.
**... - 01:07 PM Issue #1628 (Confirmed): Ongoing cleanup of SymbiFlow sv-tests (help wanted)
- SymbiFlow has a large set of System Verilog tests: https://github.com/SymbiFlow/sv-tests
With current runtime statu... - 12:13 PM Issue #1606 (Assigned): Complete string methods (starter project)
- Very good again.
+++ b/include/verilated.cpp
+#include <algorithm>
#include <cctype>
+#inclu... - 03:18 AM Issue #1606: Complete string methods (starter project)
- Thanks for the feedback.
I have updated the branch as you suggested.
Travis look fine with the change. https:/...
12/07/2019
- 09:53 PM Issue #831 (Resolved): Gate optimizer: Can't replace lvalue assignments with const var
- If there was two logic blocks that constant propagated to be identical, they cross connected, and one had a recircula...
- 08:53 PM Issue #1627: Warnings and support of array concatenation
- 1. Pushed to fixed original warning to properly point to $bits.
2. Pushed addition of unsupported warning on unpac... - 06:49 PM Issue #1626: Interface parameter circular assignment succeeds where it should not
- Pushed the test_regress/t/t_itnerface_param_loop_bad.v test with an unsupported() tag (so doesn't run).
- 06:49 PM Issue #1624: Bad parameter width error message references parameter definition instead of reference
- Pushed the test_regress/t/t_param_width_loc_bad.v test with an unsupported() tag (so doesn't run).
- 06:09 PM Issue #1623: Interface declared in parent scope can be used incorrectly
- Pushed the test_regress/t/t_interface_parent_scope_bad.v test with an unsupported() tag (so doesn't run).
This mig... - 05:58 PM Issue #1622: Wrong modport directionality accross scopes doesn't trigger an error
- Pushed the test_regress/t/t_interface_modport_dir_bad.v test with an unsupported() tag (so doesn't run).
- 05:44 PM Issue #1369 (Confirmed): Raise error / warning on continous assignment to reg
- Sorry this has been such a mess, will make another pass. Getting this right is surprisingly difficult...
- 05:41 PM Issue #1595 (Resolved): Fix interface reference tracing
- Squashed and pushed.
- 04:35 PM Issue #1618 (Closed): Travis Mail not going to authors?
- Seems reasonable for now, we can get fancier later if need to.
- 02:30 PM Issue #1618: Travis Mail not going to authors?
- Yeah, it mostly works now. Currently, you and I will get emails on any failures or transitions from failing to passi...
- 02:08 PM Issue #1618: Travis Mail not going to authors?
- Todd, Email working, can this be closed, or more to do?
- 04:27 PM Issue #1606: Complete string methods (starter project)
- Great job! Here's some comments on the patch:
Please add your name to docs/CONTRIBUTORS to acknowledge the contri... - 03:06 PM Issue #1606: Complete string methods (starter project)
- Hi
Can I tackle this item ?
I just added compare and icompare support here.
https://github.com/yTakatsukasa/veri...
12/06/2019
- 11:59 PM Issue #1595: Fix interface reference tracing
- Looks good, squash and push at will.
Thanks for the cleanups; note clang-format is messed up with #ifdefs and a fe... - 09:21 PM Issue #1595: Fix interface reference tracing
- I believe everything is handled here now:
https://github.com/toddstrader/verilator-dev/tree/iface-trace-perf
> Do... - 12:19 AM Issue #1595: Fix interface reference tracing
- Please add a new optional third arg to catName defaulting to '.'. Or, if
you prefer a new function. I'm not oppose... - 11:53 PM Issue #1625 (Closed): Unsupported warning on usage of localparam in a function
- Thanks for your contributors update.
Fixed in git towards eventual 4.024 release.
- 11:06 PM Issue #1625: Unsupported warning on usage of localparam in a function
- Easiest one first -- have this new error ready to go. Just agree to signoff on https://github.com/verilator/verilato...
- 10:42 PM Issue #1625 (Confirmed): Unsupported warning on usage of localparam in a function
- Thanks for the test.
This syntax is not supported by at least one of the big three, so Verilator is also unlikely ... - 03:32 PM Issue #1625 (Closed): Unsupported warning on usage of localparam in a function
- Verilator bug that arises when trying to use a localparam in a function. This diff (https://github.com/drissos/ve...
- 11:53 PM Issue #1624 (Confirmed): Bad parameter width error message references parameter definition instea...
- 11:52 PM Issue #1624 (Closed): Bad parameter width error message references parameter definition instead o...
- 11:16 PM Issue #1624: Bad parameter width error message references parameter definition instead of reference
- Signed off through this diff: https://github.com/drissos/verilator/commit/5d0a200c308af63ec513fe225402f36f6b7234ac
- 11:11 PM Issue #1624: Bad parameter width error message references parameter definition instead of reference
- Will do so now. Thanks again for checking it all out so quickly.
- 10:35 PM Issue #1624 (Confirmed): Bad parameter width error message references parameter definition instea...
- Thanks for the test (again), will take a look.
BTW as for your tests, thanks much for using the standard framework... - 03:28 PM Issue #1624 (Confirmed): Bad parameter width error message references parameter definition instea...
- If a variable of the wrong witdth is passed in as a parameter, verilator prints out in its warning the parameter defi...
- 11:11 PM Issue #1622: Wrong modport directionality accross scopes doesn't trigger an error
- Thanks for looking at all the issues. I'm not super familiar with the codebase, but would love to give it a try and l...
- 10:27 PM Issue #1622 (Confirmed): Wrong modport directionality accross scopes doesn't trigger an error
- Thanks for making the test case. Might you be able to look at fixing some of these? Anyhow I will also take a look.
- 03:19 PM Issue #1622 (Confirmed): Wrong modport directionality accross scopes doesn't trigger an error
- Verilator doesn't seem to be able to assert the correctness of modport directionality when it involves multiple scope...
- 10:58 PM Issue #1627 (Confirmed): Warnings and support of array concatenation
- $bits is not unsized, the spec says it's 32 bits, and that's also the size of bit_int_t.
I think Verilator is conf... - 09:26 PM Issue #1627 (Confirmed): Warnings and support of array concatenation
- Verilator provides a very misleading warning when using unsized numbers/parameters in a concatenation/replication. In...
- 10:46 PM Issue #1626 (Confirmed): Interface parameter circular assignment succeeds where it should not
- Thanks for the test. This might be a consequence of how elaboration mis-works (bug1540), but will take a look.
- 09:15 PM Issue #1626 (Confirmed): Interface parameter circular assignment succeeds where it should not
- Verilator seems to allow a circular parameter assignment between two interfaces defined in the same scope. This diff ...
- 10:30 PM Issue #1623 (Confirmed): Interface declared in parent scope can be used incorrectly
- Good suggestion & test case. I suggest we should warn on any dotted reference that resolves to something in an upper...
- 03:26 PM Issue #1623 (Confirmed): Interface declared in parent scope can be used incorrectly
- If an interface is declared in a module's parent scope, it seems as though the current scope can still use the inte...
- 10:22 PM Issue #831 (Confirmed): Gate optimizer: Can't replace lvalue assignments with const var
- Thanks for tracking it down, and to a small case no less, will take a look.
- 03:14 PM Issue #831: Gate optimizer: Can't replace lvalue assignments with const var
- We've recently come across this issue and have managed to reproduce it in a small testbench. You can find it in the l...
12/05/2019
- 05:35 PM Issue #1609: Detect and warn appripriately on intentional latches
- Great, let me know when you have something for review. I'd also suggest running it on SweRV to see if it flags anyth...
- 01:48 PM Issue #1609: Detect and warn appripriately on intentional latches
- Work in progress, but I have this basically working. I still need to generate more test cases and to also run a full ...
- 02:09 AM Issue #1621: [lint] Width Warning due to Comparison of String Parameter in Generate Statement
- Thanks for the quick reply!
I agree that this is not ideal, but unfortunately some synthesis tools have problems ... - 02:02 AM Issue #1621 (NoFixNeeded): [lint] Width Warning due to Comparison of String Parameter in Generate...
- Thanks for the report.
Due to the language origins "quotedconstants" are really packed number arrays. So the warn... - 01:48 AM Issue #1621 (NoFixNeeded): [lint] Width Warning due to Comparison of String Parameter in Generate...
- I recently ran `verilator --lint-only` on a module that has a string parameter which is used in a generate block late...
- 12:27 AM Issue #1620 (Resolved): Dotted function reference causes Internal Error
- Thanks for modifying a test to show the issue, makes it much easier.
Seemed the assertion was all that was broken....
12/04/2019
- 01:21 PM Issue #1620 (Closed): Dotted function reference causes Internal Error
- A dotted function reference through an array of instances with a non constant argument causes @Internal Error: ParseR...
- 01:11 PM Issue #1595: Fix interface reference tracing
- > Does this have to be done as another whole visitor pass?
I tried to add this to existing visitors before but it wa... - 12:12 AM Issue #1598 (Closed): Problems attempting to redefine VL_PRINTF
- Thanks for your work. Pushed to git towards eventual 4.024 release.
12/03/2019
- 11:28 PM Issue #1619 (Resolved): $value$plusargs compile error for real types (%e / %f / %g unsupported)
- Fixed in git towards eventual 4.024 release.
- 11:00 PM Issue #1619: $value$plusargs compile error for real types (%e / %f / %g unsupported)
- done
- 10:50 PM Issue #1619 (Confirmed): $value$plusargs compile error for real types (%e / %f / %g unsupported)
- Love getting bugs with patches to fix them!
Your patch looks good, just one nit, please replicate the %f test to a... - 08:12 PM Issue #1619: $value$plusargs compile error for real types (%e / %f / %g unsupported)
- Pull request: https://github.com/verilator/verilator/pull/6
- 08:02 PM Issue #1619 (Closed): $value$plusargs compile error for real types (%e / %f / %g unsupported)
- Similar to Issue #1592, the command-line processing in verilated_heavy.h lacks support for 'double':...
- 11:27 PM Issue #1592 (Resolved): $value_plusargs compile error for [1..16]-bit signals
- Fixed in git towards eventual 4.024 release.
- 08:12 PM Issue #1592: $value_plusargs compile error for [1..16]-bit signals
- Pull request: https://github.com/verilator/verilator/pull/6
- 07:45 PM Issue #1592: $value_plusargs compile error for [1..16]-bit signals
- Sorry for the delay. I was waiting to hear back from my company's legal department regarding open source contribution...
- 01:50 AM Issue #1592: $value_plusargs compile error for [1..16]-bit signals
- Would you be willing to make the changes suggested earlier (test & add your name to contributors) so this can get in ...
- 05:34 PM Issue #1595: Fix interface reference tracing
- I wasn't sure if a no-dot was possible. If you can't get it, just add an assert please.
- 03:00 PM Issue #1595: Fix interface reference tracing
- > Think you need to deal with lastDot being npos. Think its possibly valid (not just assert), consider adding a test ...
- 12:37 AM Issue #1595: Fix interface reference tracing
- From your post:
size_t nameLen = strlen("value");
nameLen += strlen(scope) + 1;
... - 03:52 PM Issue #1598: Problems attempting to redefine VL_PRINTF
- Yes, Agreed
- 12:22 PM Issue #1598: Problems attempting to redefine VL_PRINTF
- Yes, that looks like a fine place. Do you agree this (and future so don't need to ask again) contributions are open s...
- 12:05 PM Issue #1598: Problems attempting to redefine VL_PRINTF
- Just got round to this, yes, the attached patch works when combined with adding the following to the Verilator comman...
- 01:49 AM Issue #1598: Problems attempting to redefine VL_PRINTF
- Did the redefinition etc work for you? if so, can you send back a patch of what worked out? Thanks.
12/02/2019
- 09:19 PM Issue #1595: Fix interface reference tracing
- Latest updates are still in this branch:
https://github.com/toddstrader/verilator-dev/tree/iface-trace-perf
I am ... - 02:07 PM Issue #1618: Travis Mail not going to authors?
- If travis has nothing to fix this, perhaps instead of overriding email, have a end-of-run script that simply does a s...
- 01:16 PM Issue #1618 (Confirmed): Travis Mail not going to authors?
- You're right. The default Travis behavior is to email the author and committer. But if you specify an email recipie...
- 12:58 PM Issue #1618 (Closed): Travis Mail not going to authors?
- Re issue 1617:
BTW, something, maybe your email-yourself?, seems to have broken the author of the commit getting e... - 01:35 PM Issue #1616 (Closed): Intenal Error of "Multiple root modules" happens if one of sub modules is n...
- Fixed in git towards 4.024.
- 12:59 PM Issue #1617 (Closed): Assoc array adds C++11 in the codebase
- Passed in travis, thanks for the report.
Filed bug1618 for travis "BTW" above.
- 11:19 AM Issue #1617 (Confirmed): Assoc array adds C++11 in the codebase
- Sorry, that include slipped through I had added a new class instead of using array and forgot to remove the include. ...
- 11:01 AM Issue #1617 (Closed): Assoc array adds C++11 in the codebase
- The associative arrays commit has broken Travis:
https://github.com/verilator/verilator/commit/b81295230a866e38c4183...
12/01/2019
- 10:20 PM Issue #1614 (Resolved): Multiple label redefinition/parsing issue for constant functions used in ...
- Fixed in git towards eventual 4.024 release.
- 05:43 PM Issue #1615 (Closed): --output-split units documented as bytes, but appears to be closer to lines
- Fixed in git.
- 05:36 PM Issue #545 (Resolved): Support queues
- Initial queue support (using method notation, not {} notation) is in git towards eventual 4.024 release.
- 04:54 PM Issue #544 (Resolved): Support associative arrays
- Associative array support for general types, excluding [*] and pattern assignment, is in git for eventual 4.024 relea...
- 04:01 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
- Sorry, missed that, looks fine.
- 01:02 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
- m_foundTop is already in the constructor initializer list. Is it fine there or should I move it to the constructor's...
- 10:58 AM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
- Todd, thanks for fixing. Feel free to push, you just need to init m_foundTop = false in the constructor.
11/30/2019
- 04:37 PM Issue #1616 (Confirmed): Intenal Error of "Multiple root modules" happens if one of sub modules i...
- That check was overly aggressive when inlining. Here's my proposed solution:
https://github.com/toddstrader/verilat...
11/29/2019
- 11:21 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
- Thanks for the example. I'll take a look.
- 10:43 PM Issue #1616 (Closed): Intenal Error of "Multiple root modules" happens if one of sub modules is n...
- First of all, thank you very much for maintaining and evolving the great software.
I am exploring --protect-lib to... - 08:13 PM Issue #1595: Fix interface reference tracing
- Yeah, I'll just need some C str functions in the generated code to concatenate the two parts of the name. I'll do th...
- 07:20 PM Issue #1595: Fix interface reference tracing
- I don't understand the need to change the include/ headers. I would think calling these decl functions with the prope...
- 05:14 PM Issue #1595: Fix interface reference tracing
- What I've ended up on is creating a new AstIntfRef which is a child of AstCell nodes which are interfaces. These alw...
11/27/2019
- 02:07 PM Issue #1369: Raise error / warning on continous assignment to reg
- Warning about assigning to output reg does not work for me. I'm using tag 4.022 without success....
- 11:12 AM Issue #1615 (Confirmed): --output-split units documented as bytes, but appears to be closer to lines
- Thanks, will update these in the docs.
Output-split is roughly number of statements. - 10:58 AM Issue #1615: --output-split units documented as bytes, but appears to be closer to lines
- It would also be worth mentioning that VM_PARALLEL_BUILDS needs to be set to 1 on the make command line to exploit pa...
- 10:29 AM Issue #1615 (Closed): --output-split units documented as bytes, but appears to be closer to lines
- The manual states the units of the --output-split option as bytes in both the summary and the full description, but i...
11/26/2019
- 06:44 PM Issue #1614 (Confirmed): Multiple label redefinition/parsing issue for constant functions used in...
- Will take a look.
You might also be able to work around it by replacing the return with "min=..."
11/25/2019
- 03:24 PM Issue #1614 (Closed): Multiple label redefinition/parsing issue for constant functions used in co...
- Minimal case below...
11/23/2019
- 01:31 AM Issue #1572: Extend --protect-lib for foreign/embedded module use
- For those looking to try embedding without protection, for just for experimentation, use a recent git version and try...
11/22/2019
- 11:13 PM Issue #1613 (Confirmed): verilator %Warning-WIDTH false positive
- You're right, an easy cross check:
$display("%d", $size(o_dec_table.dec_len));
16
What looks to be... - 08:35 PM Issue #1613: verilator %Warning-WIDTH false positive
- I think what I said above is consistent with IEEE 1800-2017 7.4.5 which says (among other things), "A subarray is an ...
- 07:44 PM Issue #1613: verilator %Warning-WIDTH false positive
- does ...
- 05:21 PM Issue #1613: verilator %Warning-WIDTH false positive
- The rightmost index of dec_len is 31:0, meaning it needs 6 bits to index into. Your cur_bit_len as you indicate is on...
- 03:28 PM Issue #1613 (Confirmed): verilator %Warning-WIDTH false positive
- excerpt of file.sv......
- 08:35 PM Issue #1612 (Closed): New VPI tests failing clang and Trusty builds
- Cron seems happy now:
https://travis-ci.com/verilator/verilator/builds/137738748
11/21/2019
- 11:43 PM Issue #1612 (Confirmed): New VPI tests failing clang and Trusty builds
- Fixed, had uninit variable. Leaving open for now to see if Travis is happy.
Also added an error when test core du... - 12:57 PM Issue #1612 (Closed): New VPI tests failing clang and Trusty builds
- Appears similar to bug1611. See:
https://travis-ci.com/verilator/verilator/builds/137544069
Affects --vlt and --...
11/20/2019
- 11:49 PM Issue #1609 (Feature): Detect and warn appripriately on intentional latches
- 11:48 PM Issue #1609 (Assigned): Detect and warn appripriately on intentional latches
- Great, would be awesome to get this in.
The sensitivity list will at that point have some elements with combo on i... - 01:57 PM Issue #1609: Detect and warn appripriately on intentional latches
- To ignore intentional standalone latches I think I need to update class ActiveDlyVisitor to supress the warning if th...
- 03:36 AM Issue #1609: Detect and warn appripriately on intentional latches
- Not sure I'm interpreting the question correctly, but...
Verilator doesn't presently identify self-identify latche... - 11:58 AM Issue #1611 (Closed): New VPI tests failing under --vltmt
- Thanks, worked for me as builds went in different order, but should have noticed that code.
Fix pushed.
- 10:40 AM Issue #1611 (Closed): New VPI tests failing under --vltmt
- Two tests from this PR are failing CI under --vltmt:
https://github.com/verilator/verilator/pull/5
See:
https://... - 03:21 AM Issue #1595: Fix interface reference tracing
- You can't have cells point to varscopes as it's a many-to-one arrangement, which is why scopes exist in the first pla...
- 12:24 AM Issue #1608 (Resolved): Strange dotted expression makes Verilator hang, but print correct error m...
- Thanks for the report.
Fixed in git towards eventual 4.024 release.
11/19/2019
- 03:30 PM Issue #1609 (Feature): Detect and warn appripriately on intentional latches
- According to Cummings:
"Guideline #2: When modeling latches, use nonblocking assignments."
However, as I'm sure y... - 12:39 PM Issue #1595: Fix interface reference tracing
- I'm now thinking that the cleaner way to do this is to TraceDecl the entire interface. That way we can emit a TraceD...
- 10:37 AM Issue #1608 (Closed): Strange dotted expression makes Verilator hang, but print correct error mes...
- The following module makes Verilator hang...
- 03:11 AM Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
11/18/2019
- 10:04 AM Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
- A pull is out against GTKwave. Once this completes:
- Move personal script to compare GTKwave include upstream to ...
11/17/2019
- 06:39 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- Wilson Snyder wrote:
> All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of... - 11:42 AM Issue #1605: for loop initialisation clause skipped
- Thanks for fixing it so quickly.
- 11:36 AM Issue #1604: Unknown node in split color() map on empty if
- Thanks for fixing it. I had not attached any significance to them being unused; however, there are three instances o...
- 09:58 AM Issue #1606 (Resolved): Complete string methods (starter project)
- Implement the built-in string methods that are remaining:
- atobin, atohex, atoi, atooct, atoreal: Become a scanf....
11/16/2019
- 10:24 PM Issue #1604 (Resolved): Unknown node in split color() map on empty if
- Thanks for the good test case.
This was caused by your outputs (rx & ry) never being used, not sure if you noticed... - 08:18 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of the bits that are speci...
- 07:25 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- Wilson Snyder wrote:
> >But it doesn't capture internal behavioral source/destination
>
> It does, for example s...
11/15/2019
- 11:38 PM Issue #1604 (Confirmed): Unknown node in split color() map on empty if
- Will require some research. The irony is the point of the broken optimization is to transform it into exactly what y...
- 10:35 PM Issue #1604 (Closed): Unknown node in split color() map on empty if
- ...
- 11:25 PM Issue #1605 (Resolved): for loop initialisation clause skipped
- Sorry, that's nasty and should have been caught earlier, so fixing immediately.
FWIW "for (i=1; 0; )" was tested, ... - 10:47 PM Issue #1605 (Closed): for loop initialisation clause skipped
- The body of the first for loop in this code never executes because the condition clause is always false; however it s...
- 08:48 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- >But it doesn't capture internal behavioral source/destination
It does, for example see the varref (references to... - 08:41 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
- Wilson Snyder wrote:
> Verilog-perl has some of this information, but from what you describe I would suggest first l... - 09:36 AM Issue #1598: Problems attempting to redefine VL_PRINTF
- Thanks for the pointers, I will persevere with that aproach and try and get a patch out ...
- 08:39 AM Issue #1598 (Confirmed): Problems attempting to redefine VL_PRINTF
- Originally VL_PRINTF was intended to be overridden in a .mk file which overrode the default verilator.mk file. For t...
- 09:08 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
- This is to protect against what in some cases may become:
int foo;
void foo();
which causes a mess of course. ... - 02:11 AM Issue #1603: Statement label should be allowed to be a duplicate of a parameter
- Ok well that formatting failed - trying again:
This syntax is not allowed by verilator:... - 02:09 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
- This syntax is not allowed by verilator:...
- 08:02 AM Issue #1595 (Assigned): Fix interface reference tracing
- 08:02 AM Issue #1602 (Assigned): Investigate Travis CMake error message
- 08:01 AM Issue #1601 (Confirmed): Add SystemC to Travis
- Hopefully someone has a pre-built package otherwise we'll need to build it, as too slow/unstable to build every time....
- 07:59 AM Issue #1600 (Confirmed): Add vcddiff to Travis
- 07:59 AM Issue #1600: Add vcddiff to Travis
- Might want to put a binary somewhere as this almost never changes.
11/14/2019
- 11:09 PM Issue #1602 (Assigned): Investigate Travis CMake error message
- I've only seen this in Travis (and maybe only with Trusty). It was showing up in the logs because of a probably unre...
- 11:06 PM Issue #1601 (Confirmed): Add SystemC to Travis
- SystemC tests are being skipped right now.
- 11:05 PM Issue #1600 (Closed): Add vcddiff to Travis
- A number of tests are not running because this is missing.
- 11:04 PM Issue #1596 (Resolved): Travis tweaks
- Squashed and pushed to both repos. I added some Makefile logic to examples/xml_py to skip the example if Python < 3....
- 09:04 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
- Verilog-perl has some of this information, but from what you describe I would suggest first looking at Verilator's --...
- 06:40 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
- I have trying to form a signal connectivity Parser within a Module file. It Can read (one or multiple) Verilog files ...
- 03:27 PM Issue #1598 (Closed): Problems attempting to redefine VL_PRINTF
- I need my verilated model to call something other than printf to perform output $display, and the intended way to do ...
11/13/2019
- 10:56 PM Issue #1596: Travis tweaks
- That example isn't terribly important. I suggest I just only run it if python is new enough, rather than take the 3 ...
- 09:38 PM Issue #1596: Travis tweaks
- The other option here is to install Python 3.5 on the Trusty image. This is the latest version of Python3 that Ubunt...
- 01:28 PM Issue #1596: Travis tweaks
- I think we should aim to allow 14.04, or at least plan to until we find something painful.
Thanks for diagnosing e... - 01:24 PM Issue #1596: Travis tweaks
- Great, I'll keep that in mind. I've gone down a bit of a rabbit hole here and am cleaning up a few more things. One...
- 09:39 PM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- I'm not sure if you mean that the warning can be disabled for my case or the fundamental issue can be fixed for my ca...
- 12:34 AM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- Good point, raised to normal. Perhaps if I provide some pointers you could attempt a patch to the warning (which sho...
- 02:15 PM Issue #1597 (AskedReporter): building verilator from source package
- By setting VERILATOR_ROOT that overrides the default you set for prefix, just don't set that and it should work, let ...
- 01:59 PM Issue #1597 (NoFixNeeded): building verilator from source package
- Dear Community,
I've compiled the Verilator from scratch.
Untar the verilator-4.016.tgz.
cd /home/myhome/myloc...
11/12/2019
- 10:17 PM Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- I am running into this problem very frequently with RTL that extensively uses packed structs. For instance this does...
- 11:29 AM Issue #1596: Travis tweaks
- Looks good. Feel free to continue to ask, but also feel free to push any travis or other changes you feel reasonably...
- 10:38 AM Issue #1596 (Closed): Travis tweaks
- See:
https://github.com/toddstrader/verilator-dev/tree/travis-tweaks
and:
https://github.com/toddstrader/verilator...
11/11/2019
- 01:34 PM Issue #1595: Fix interface reference tracing
- The scopes are known once V3Scope completes, so yes they are known.
I'm not sure what the easiest way to know from... - 01:08 PM Issue #1595 (Closed): Fix interface reference tracing
- I discovered that my commit for bug1594 is not yet working (and unfortunately escaped into 4.022). The problem is th...
11/10/2019
- 07:30 PM Issue #1519 (Closed): Benchmark --protect-lib runtime
- In 4.022.
(& thanks for all your work in this release) - 07:29 PM Issue #1581 (Closed): Ranges starting with zero result in unsigned/constant warning
- In 4.022.
- 07:28 PM Issue #1490 (Closed): Add an option to create a DPI protected library
- In 4.022.
- 07:28 PM Issue #1363 (Closed): CMake support
- In 4.022.
- 07:28 PM Issue #1521 (Closed): Add --protect-ids to enhance --protect-lib obfuscation
- In 4.022.
- 07:28 PM Issue #1315 (Closed): Using an array in a function called from a parameter
- In 4.022.
- 12:27 AM Issue #1315: Using an array in a function called from a parameter
- Could you look again at bug1484 and maybe add it to the regression? It doesn't work with the basic support that was c...
- 07:28 PM Issue #1594 (Closed): Add interface port visibility in traces
- In 4.022.
- 07:28 PM Issue #1535 (Closed): Double quotes in -f option file
- In 4.022.
- 07:28 PM Issue #1570 (Closed): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpack ...
- In 4.022.
- 07:27 PM Verilator 4.022 Released
- Verilator 4.022 2019-11-10
** Add --protect-lib, bug1490. [Todd Strader]
** Add cmake support, bug1363. [... - 01:43 AM Issue #1484: Parameter of an array of enumeration values breaks conditionals inside a generate block
- Silly mistake :( Thank you for looking at it!
- 01:32 AM Issue #1484: Parameter of an array of enumeration values breaks conditionals inside a generate block
- Note bug1315 is fixed in git, now this example fails with
%Error: t/t_param_array6.v:58: Illegal assignment of ...
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