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Activity

From 12/11/2019 to 01/09/2020

12/29/2019

06:26 PM Usage: RE: Verilator + SWIG = Python wrapper?
Actually, verilator now has built in support for exporting a Python class here.
https://github.com/patstew/verilator...
Yehowshua Immanuel

12/28/2019

06:13 PM Usage: RE: Verilator + SWIG = Python wrapper?
It looks like this also works quite well.
https://github.com/csail-csg/pyverilator
Yehowshua Immanuel

12/18/2019

02:39 PM Usage: RE: Support for modeling metastability on setup/hold time violation
Verilator doesn't model time delays, nor support SDF timing annotation. Icarus might be able to, not sure.
BTW mo...
Wilson Snyder
02:06 PM Usage: Support for modeling metastability on setup/hold time violation
I'm looking for a way to accurately model setup time violations for a flip flop during simulation. Currently, I'm us... Niraj Menon

12/11/2019

10:08 PM Usage: RE: Verilog 2001 config as an alternate to using non standard `uselib
I don't think config is widely supported, we'll look at adding `uselib.
Wilson Snyder
08:37 PM Usage: Verilog 2001 config as an alternate to using non standard `uselib

In verilog I only know of 2 methods to deal with the problem of multiple modules with same name in different librar...
Frederic Antonin
11:56 AM Usage: RE: it is any possible to make verilator case-insensitive ?
Verilog is a case sensitive language, so I'm reluctant to add such an option as it would encourage standard violation... Wilson Snyder
06:09 AM Usage: it is any possible to make verilator case-insensitive ?
For some reason,I use the uppercase letters as module name,like ABC,but its file named abc.v.
But it seems that veri...
Jacob Liang
 

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