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Activity

From 11/14/2019 to 12/13/2019

Today

03:55 PM Issue #1514: Switch for file to read public signals from
I have started basic prototyping of this feature here: https://github.com/wallento/verilator/tree/vlt-attrs
I beli...
Stefan Wallentowitz
03:50 PM Issue #1567: Cocotb Integration
Nearly there, #1636 is the last one we need for the basic examples. The merge progress can be tracked here: https://g... Stefan Wallentowitz
12:16 PM Issue #1636 (Assigned): Add vpiTimeUnit and allow to specify time as string
Seems reasonable. The real fix which might replace some of this is to add correct time support. This is on the roadm... Wilson Snyder
01:54 AM Issue #1634 (Resolved): `uselib error with Verilator
Fixed in git to ignore until end-of-line.
Wilson Snyder

12/12/2019

02:15 PM Issue #1636: Add vpiTimeUnit and allow to specify time as string
https://github.com/wallento/verilator/tree/issue-1636 Stefan Wallentowitz
02:14 PM Issue #1636 (Assigned): Add vpiTimeUnit and allow to specify time as string
Add vpiTimeUnit, despite there is not much value in it for Verilator, but for completeness.

Allow to specify t...
Stefan Wallentowitz
01:21 PM Issue #1634: `uselib error with Verilator
I'm afraid this if beyond my coding skills.
I tried to look into verilog.y to see how other pre processors are trea...
Frederic Antonin
12:56 PM Issue #1635 (Closed): Documentation fixes
Sounds good. Also, done. Todd Strader
11:06 AM Issue #1635: Documentation fixes
Yes, it should be as you suggest. Also please add `verilog if absent.
Push at will (any doc cleanup ever ;)
Wilson Snyder
10:39 AM Issue #1635 (Closed): Documentation fixes
I found four instances of "the the" in the --help and have repaired them here:
https://github.com/toddstrader/verila...
Todd Strader

12/11/2019

10:16 PM Issue #1631 (Resolved): -Wno-lint disables LITENDIAN and allows silent generation of code inconsi...
Excellent, thanks.
Pushed to git towards eventual 4.026 release.
Wilson Snyder
12:47 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
Patch and new test attached
(test pass with --vcs confirmed, test fail without patch confirmed)
Julien Margetts
11:32 AM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
Will do.
github username is jcrmargetts
Julien Margetts
10:11 PM Issue #1634 (Feature): `uselib error with Verilator
Ok, seems reasonable to ignore this then, can you look at patching this?
1. Add a test to test_regress/t
2. Updat...
Wilson Snyder
06:45 PM Issue #1634: `uselib error with Verilator
`uselib is a work around for a Verilog problem. It is supported by both Mentor and Cadence simulators.
Verilog doe...
Frederic Antonin
05:59 PM Issue #1634 (Closed): `uselib error with Verilator
`uselib not only is not supported, it isn't part of the language, and I don't know what it is and don't see much from... Wilson Snyder
05:30 PM Issue #1634 (Resolved): `uselib error with Verilator
I have some code that use the following construct before a module instantiation.... Frederic Antonin
12:05 AM Issue #1633 (Closed): Gtkwave update breaks verilator_ext_tests
I had added the ext test to catch this sort of delta.
Gtkwave is now in github, that repo is the new master.
Un...
Wilson Snyder

12/10/2019

10:38 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
Patch looks good, can you please also update one of the test_regress tests to show the issue so it doesn't break in t... Wilson Snyder
02:57 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
No new failures in regression Julien Margetts
12:56 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
This fixes it:
Regression in progress...
Julien Margetts
11:53 AM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
Ok, Ill take a look Julien Margetts
12:58 AM Issue #1631 (Confirmed): -Wno-lint disables LITENDIAN and allows silent generation of code incons...
Ok, seems reasonable to clean this up then.
Perhaps you could try to put together a patch? The code that does this...
Wilson Snyder
10:33 PM Issue #1632 (NoFixNeeded): %m format argument to $display causes error: ‘SCOPE_OTHER’ is not a me...
Glad it got resolved.
Wilson Snyder
12:29 PM Issue #1632: %m format argument to $display causes error: ‘SCOPE_OTHER’ is not a member of ‘Veril...
My bad.
Hadn't done a make install so compile was picking up 4.018 headers.
Appologies for the noise
Julien Margetts
12:03 PM Issue #1632: %m format argument to $display causes error: ‘SCOPE_OTHER’ is not a member of ‘Veril...
Works for me, what is your command line?
Wilson Snyder
10:43 AM Issue #1632 (NoFixNeeded): %m format argument to $display causes error: ‘SCOPE_OTHER’ is not a me...
This issue arrived with 4.020 and I think may have been introduced by the patch for Issue 1469
Test code:...
Julien Margetts
10:18 PM Issue #1633 (Closed): Gtkwave update breaks verilator_ext_tests
t_gtkwave_diff is failing because gtkwave has updated fstapi.[ch]:
https://travis-ci.com/verilator/verilator_ext_tes...
Todd Strader
11:17 AM Issue #1606: Complete string methods (starter project)
Thanks a lot!
Now I understand this project better.
I will work on getc/putc/substr towards this weekend.
Yutetsu TAKATSUKASA
12:20 AM Issue #1606: Complete string methods (starter project)
This is merged, great work. FYI I made two minor changes, fixed some spacing to be closer to clang-format, and avoid... Wilson Snyder
10:31 AM Issue #1600 (Closed): Add vcddiff to Travis
Ideally I would have created a PPA for this (I found one, but it doesn't work for some reason). However, I've never ... Todd Strader
12:56 AM Issue #1630 (NoFixNeeded): Not able to force values on wires in positive edge of clock cycle
Making a signal public doesn't act like a force, rather it makes the storage that's already there able to be accessed... Wilson Snyder

12/09/2019

06:55 PM Issue #1590: Fuzzer: Segfault on parameter as generate condition
Yes, that change can be made. Unfortunately though, this makes it unlikely to find anything. The fuzzer itself tend... Eric Rippey
06:13 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
VCS and NCSIM behave the same. I do not have access to Modelsim and it does not appear to be an option on edaplaygrou... Julien Margetts
05:33 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
LITENDIAN was intended not to change the results.
Can you please run this on all of the big-3 e.g. on edaplaygroun...
Wilson Snyder
03:14 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
A brief scan of the LRM has left me still unsure of what the correct behaviour should be Julien Margetts
03:12 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
Actually, the difference between VCS and Verilator is that when connecting the elements of the +array+ 'cval' to the ... Julien Margetts
01:55 PM Issue #1631: -Wno-lint disables LITENDIAN and allows silent generation of code inconsistent with ...
Changing only the declaration of inc from an N-bit LE vector, to a an N element LE array, makes the output match, and... Julien Margetts
01:33 PM Issue #1631 (Resolved): -Wno-lint disables LITENDIAN and allows silent generation of code inconsi...
The manual states "Ranges must be big-bit-endian" so I think LITENDIAN should not be a member of lintError() and shou... Julien Margetts
05:40 PM Issue #1606: Complete string methods (starter project)
I'm sorry, I misread the added includes as being in the .h file. Adding includes is fine in the verilated.cpp file.
...
Wilson Snyder
02:39 PM Issue #1606: Complete string methods (starter project)
Thanks again for the comments.
I have updated the branch other than the following item.
> Adding these will slow ...
Yutetsu TAKATSUKASA
09:44 AM Issue #1630: Not able to force values on wires in positive edge of clock cycle
I ran verilator with the following commands:
verilator -Wall --cc --trace counter.v --exe tb_counter.cpp
make -...
Pavan Talluri
09:40 AM Issue #1630 (NoFixNeeded): Not able to force values on wires in positive edge of clock cycle
For a simple counter module, i was trying to force some wires from the test bench.
I declared the wires as public in...
Pavan Talluri
02:55 AM Issue #1629 (WillNotFix): Optimize wide vectors to use 64 bit entries
This is to capture notes on a performance experiment.
Verilator uses arrays of 32-bit words for signals over 64 bi...
Wilson Snyder

12/08/2019

01:13 PM Issue #1596 (Closed): Travis tweaks
In 4.024.
Wilson Snyder
01:13 PM Issue #1604 (Closed): Unknown node in split color() map on empty if
In 4.024.
Wilson Snyder
01:12 PM Issue #1605 (Closed): for loop initialisation clause skipped
In 4.024.
For additional support related to this please file new bug.
Wilson Snyder
01:12 PM Issue #1608 (Closed): Strange dotted expression makes Verilator hang, but print correct error mes...
In 4.024.
For additional support related to this please file new bug.
Wilson Snyder
01:12 PM Issue #544 (Closed): Support associative arrays
In 4.024.
For additional support related to this please file new bug.
Wilson Snyder
01:12 PM Issue #545 (Closed): Support queues
In 4.024.
For additional support related to this please file new bug.
Wilson Snyder
01:11 PM Issue #1614 (Closed): Multiple label redefinition/parsing issue for constant functions used in co...
In 4.024.
Wilson Snyder
01:11 PM Issue #1592 (Closed): $value_plusargs compile error for [1..16]-bit signals
In 4.024.
Wilson Snyder
01:11 PM Issue #1619 (Closed): $value$plusargs compile error for real types (%e / %f / %g unsupported)
In 4.024.
Wilson Snyder
01:11 PM Issue #1620 (Closed): Dotted function reference causes Internal Error
In 4.024.
Wilson Snyder
01:11 PM Issue #1595 (Closed): Fix interface reference tracing
In 4.024.
Wilson Snyder
01:11 PM Issue #831 (Closed): Gate optimizer: Can't replace lvalue assignments with const var
In 4.024.
Wilson Snyder
01:07 PM Issue #1628 (Confirmed): Ongoing cleanup of SymbiFlow sv-tests (help wanted)
SymbiFlow has a large set of System Verilog tests: https://github.com/SymbiFlow/sv-tests
With current runtime statu...
Wilson Snyder
12:13 PM Issue #1606 (Assigned): Complete string methods (starter project)
Very good again.
+++ b/include/verilated.cpp
+#include <algorithm>
#include <cctype>
+#inclu...
Wilson Snyder
03:18 AM Issue #1606: Complete string methods (starter project)
Thanks for the feedback.
I have updated the branch as you suggested.
Travis look fine with the change. https:/...
Yutetsu TAKATSUKASA

12/07/2019

09:53 PM Issue #831 (Resolved): Gate optimizer: Can't replace lvalue assignments with const var
If there was two logic blocks that constant propagated to be identical, they cross connected, and one had a recircula... Wilson Snyder
08:53 PM Issue #1627: Warnings and support of array concatenation
1. Pushed to fixed original warning to properly point to $bits.
2. Pushed addition of unsupported warning on unpac...
Wilson Snyder
06:49 PM Issue #1626: Interface parameter circular assignment succeeds where it should not
Pushed the test_regress/t/t_itnerface_param_loop_bad.v test with an unsupported() tag (so doesn't run). Wilson Snyder
06:49 PM Issue #1624: Bad parameter width error message references parameter definition instead of reference
Pushed the test_regress/t/t_param_width_loc_bad.v test with an unsupported() tag (so doesn't run).
Wilson Snyder
06:09 PM Issue #1623: Interface declared in parent scope can be used incorrectly
Pushed the test_regress/t/t_interface_parent_scope_bad.v test with an unsupported() tag (so doesn't run).
This mig...
Wilson Snyder
05:58 PM Issue #1622: Wrong modport directionality accross scopes doesn't trigger an error
Pushed the test_regress/t/t_interface_modport_dir_bad.v test with an unsupported() tag (so doesn't run).
Wilson Snyder
05:44 PM Issue #1369 (Confirmed): Raise error / warning on continous assignment to reg
Sorry this has been such a mess, will make another pass. Getting this right is surprisingly difficult...
Wilson Snyder
05:41 PM Issue #1595 (Resolved): Fix interface reference tracing
Squashed and pushed. Todd Strader
04:35 PM Issue #1618 (Closed): Travis Mail not going to authors?
Seems reasonable for now, we can get fancier later if need to.
Wilson Snyder
02:30 PM Issue #1618: Travis Mail not going to authors?
Yeah, it mostly works now. Currently, you and I will get emails on any failures or transitions from failing to passi... Todd Strader
02:08 PM Issue #1618: Travis Mail not going to authors?
Todd, Email working, can this be closed, or more to do? Wilson Snyder
04:27 PM Issue #1606: Complete string methods (starter project)
Great job! Here's some comments on the patch:
Please add your name to docs/CONTRIBUTORS to acknowledge the contri...
Wilson Snyder
03:06 PM Issue #1606: Complete string methods (starter project)
Hi
Can I tackle this item ?
I just added compare and icompare support here.
https://github.com/yTakatsukasa/veri...
Yutetsu TAKATSUKASA

12/06/2019

11:59 PM Issue #1595: Fix interface reference tracing
Looks good, squash and push at will.
Thanks for the cleanups; note clang-format is messed up with #ifdefs and a fe...
Wilson Snyder
09:21 PM Issue #1595: Fix interface reference tracing
I believe everything is handled here now:
https://github.com/toddstrader/verilator-dev/tree/iface-trace-perf
> Do...
Todd Strader
12:19 AM Issue #1595: Fix interface reference tracing
Please add a new optional third arg to catName defaulting to '.'. Or, if
you prefer a new function. I'm not oppose...
Wilson Snyder
11:53 PM Issue #1625 (Closed): Unsupported warning on usage of localparam in a function
Thanks for your contributors update.
Fixed in git towards eventual 4.024 release.
Wilson Snyder
11:06 PM Issue #1625: Unsupported warning on usage of localparam in a function
Easiest one first -- have this new error ready to go. Just agree to signoff on https://github.com/verilator/verilato... Wilson Snyder
10:42 PM Issue #1625 (Confirmed): Unsupported warning on usage of localparam in a function
Thanks for the test.
This syntax is not supported by at least one of the big three, so Verilator is also unlikely ...
Wilson Snyder
03:32 PM Issue #1625 (Closed): Unsupported warning on usage of localparam in a function
Verilator bug that arises when trying to use a localparam in a function. This diff (https://github.com/drissos/ve... Driss Hafdi
11:53 PM Issue #1624 (Confirmed): Bad parameter width error message references parameter definition instea...
Wilson Snyder
11:52 PM Issue #1624 (Closed): Bad parameter width error message references parameter definition instead o...
Wilson Snyder
11:16 PM Issue #1624: Bad parameter width error message references parameter definition instead of reference
Signed off through this diff: https://github.com/drissos/verilator/commit/5d0a200c308af63ec513fe225402f36f6b7234ac Driss Hafdi
11:11 PM Issue #1624: Bad parameter width error message references parameter definition instead of reference
Will do so now. Thanks again for checking it all out so quickly. Driss Hafdi
10:35 PM Issue #1624 (Confirmed): Bad parameter width error message references parameter definition instea...
Thanks for the test (again), will take a look.
BTW as for your tests, thanks much for using the standard framework...
Wilson Snyder
03:28 PM Issue #1624 (Confirmed): Bad parameter width error message references parameter definition instea...
If a variable of the wrong witdth is passed in as a parameter, verilator prints out in its warning the parameter defi... Driss Hafdi
11:11 PM Issue #1622: Wrong modport directionality accross scopes doesn't trigger an error
Thanks for looking at all the issues. I'm not super familiar with the codebase, but would love to give it a try and l... Driss Hafdi
10:27 PM Issue #1622 (Confirmed): Wrong modport directionality accross scopes doesn't trigger an error
Thanks for making the test case. Might you be able to look at fixing some of these? Anyhow I will also take a look.
Wilson Snyder
03:19 PM Issue #1622 (Confirmed): Wrong modport directionality accross scopes doesn't trigger an error
Verilator doesn't seem to be able to assert the correctness of modport directionality when it involves multiple scope... Driss Hafdi
10:58 PM Issue #1627 (Confirmed): Warnings and support of array concatenation
$bits is not unsized, the spec says it's 32 bits, and that's also the size of bit_int_t.
I think Verilator is conf...
Wilson Snyder
09:26 PM Issue #1627 (Confirmed): Warnings and support of array concatenation
Verilator provides a very misleading warning when using unsized numbers/parameters in a concatenation/replication. In... Driss Hafdi
10:46 PM Issue #1626 (Confirmed): Interface parameter circular assignment succeeds where it should not
Thanks for the test. This might be a consequence of how elaboration mis-works (bug1540), but will take a look.
Wilson Snyder
09:15 PM Issue #1626 (Confirmed): Interface parameter circular assignment succeeds where it should not
Verilator seems to allow a circular parameter assignment between two interfaces defined in the same scope. This diff ... Driss Hafdi
10:30 PM Issue #1623 (Confirmed): Interface declared in parent scope can be used incorrectly
Good suggestion & test case. I suggest we should warn on any dotted reference that resolves to something in an upper... Wilson Snyder
03:26 PM Issue #1623 (Confirmed): Interface declared in parent scope can be used incorrectly
If an interface is declared in a module's parent scope, it seems as though the current scope can still use the inte... Driss Hafdi
10:22 PM Issue #831 (Confirmed): Gate optimizer: Can't replace lvalue assignments with const var
Thanks for tracking it down, and to a small case no less, will take a look. Wilson Snyder
03:14 PM Issue #831: Gate optimizer: Can't replace lvalue assignments with const var
We've recently come across this issue and have managed to reproduce it in a small testbench. You can find it in the l... Driss Hafdi

12/05/2019

05:35 PM Issue #1609: Detect and warn appripriately on intentional latches
Great, let me know when you have something for review. I'd also suggest running it on SweRV to see if it flags anyth... Wilson Snyder
01:48 PM Issue #1609: Detect and warn appripriately on intentional latches
Work in progress, but I have this basically working. I still need to generate more test cases and to also run a full ... Julien Margetts
02:09 AM Issue #1621: [lint] Width Warning due to Comparison of String Parameter in Generate Statement
Thanks for the quick reply!
I agree that this is not ideal, but unfortunately some synthesis tools have problems ...
Michael Schaffner
02:02 AM Issue #1621 (NoFixNeeded): [lint] Width Warning due to Comparison of String Parameter in Generate...
Thanks for the report.
Due to the language origins "quotedconstants" are really packed number arrays. So the warn...
Wilson Snyder
01:48 AM Issue #1621 (NoFixNeeded): [lint] Width Warning due to Comparison of String Parameter in Generate...
I recently ran `verilator --lint-only` on a module that has a string parameter which is used in a generate block late... Michael Schaffner
12:27 AM Issue #1620 (Resolved): Dotted function reference causes Internal Error
Thanks for modifying a test to show the issue, makes it much easier.
Seemed the assertion was all that was broken....
Wilson Snyder

12/04/2019

01:21 PM Issue #1620 (Closed): Dotted function reference causes Internal Error
A dotted function reference through an array of instances with a non constant argument causes @Internal Error: ParseR... Rich Porter
01:11 PM Issue #1595: Fix interface reference tracing
> Does this have to be done as another whole visitor pass?
I tried to add this to existing visitors before but it wa...
Todd Strader
12:12 AM Issue #1598 (Closed): Problems attempting to redefine VL_PRINTF
Thanks for your work. Pushed to git towards eventual 4.024 release.
Wilson Snyder

12/03/2019

11:28 PM Issue #1619 (Resolved): $value$plusargs compile error for real types (%e / %f / %g unsupported)
Fixed in git towards eventual 4.024 release.
Wilson Snyder
11:00 PM Issue #1619: $value$plusargs compile error for real types (%e / %f / %g unsupported)
done Garrett Smith
10:50 PM Issue #1619 (Confirmed): $value$plusargs compile error for real types (%e / %f / %g unsupported)
Love getting bugs with patches to fix them!
Your patch looks good, just one nit, please replicate the %f test to a...
Wilson Snyder
08:12 PM Issue #1619: $value$plusargs compile error for real types (%e / %f / %g unsupported)
Pull request: https://github.com/verilator/verilator/pull/6 Garrett Smith
08:02 PM Issue #1619 (Closed): $value$plusargs compile error for real types (%e / %f / %g unsupported)
Similar to Issue #1592, the command-line processing in verilated_heavy.h lacks support for 'double':... Garrett Smith
11:27 PM Issue #1592 (Resolved): $value_plusargs compile error for [1..16]-bit signals
Fixed in git towards eventual 4.024 release.
Wilson Snyder
08:12 PM Issue #1592: $value_plusargs compile error for [1..16]-bit signals
Pull request: https://github.com/verilator/verilator/pull/6 Garrett Smith
07:45 PM Issue #1592: $value_plusargs compile error for [1..16]-bit signals
Sorry for the delay. I was waiting to hear back from my company's legal department regarding open source contribution... Garrett Smith
01:50 AM Issue #1592: $value_plusargs compile error for [1..16]-bit signals
Would you be willing to make the changes suggested earlier (test & add your name to contributors) so this can get in ... Wilson Snyder
05:34 PM Issue #1595: Fix interface reference tracing
I wasn't sure if a no-dot was possible. If you can't get it, just add an assert please.
Wilson Snyder
03:00 PM Issue #1595: Fix interface reference tracing
> Think you need to deal with lastDot being npos. Think its possibly valid (not just assert), consider adding a test ... Todd Strader
12:37 AM Issue #1595: Fix interface reference tracing
From your post:
size_t nameLen = strlen("value");
nameLen += strlen(scope) + 1;
...
Wilson Snyder
03:52 PM Issue #1598: Problems attempting to redefine VL_PRINTF
Yes, Agreed Julien Margetts
12:22 PM Issue #1598: Problems attempting to redefine VL_PRINTF
Yes, that looks like a fine place. Do you agree this (and future so don't need to ask again) contributions are open s... Wilson Snyder
12:05 PM Issue #1598: Problems attempting to redefine VL_PRINTF
Just got round to this, yes, the attached patch works when combined with adding the following to the Verilator comman... Julien Margetts
01:49 AM Issue #1598: Problems attempting to redefine VL_PRINTF
Did the redefinition etc work for you? if so, can you send back a patch of what worked out? Thanks. Wilson Snyder

12/02/2019

09:19 PM Issue #1595: Fix interface reference tracing
Latest updates are still in this branch:
https://github.com/toddstrader/verilator-dev/tree/iface-trace-perf
I am ...
Todd Strader
02:07 PM Issue #1618: Travis Mail not going to authors?
If travis has nothing to fix this, perhaps instead of overriding email, have a end-of-run script that simply does a s... Wilson Snyder
01:16 PM Issue #1618 (Confirmed): Travis Mail not going to authors?
You're right. The default Travis behavior is to email the author and committer. But if you specify an email recipie... Todd Strader
12:58 PM Issue #1618 (Closed): Travis Mail not going to authors?
Re issue 1617:
BTW, something, maybe your email-yourself?, seems to have broken the author of the commit getting e...
Wilson Snyder
01:35 PM Issue #1616 (Closed): Intenal Error of "Multiple root modules" happens if one of sub modules is n...
Fixed in git towards 4.024. Todd Strader
12:59 PM Issue #1617 (Closed): Assoc array adds C++11 in the codebase
Passed in travis, thanks for the report.
Filed bug1618 for travis "BTW" above.
Wilson Snyder
11:19 AM Issue #1617 (Confirmed): Assoc array adds C++11 in the codebase
Sorry, that include slipped through I had added a new class instead of using array and forgot to remove the include. ... Wilson Snyder
11:01 AM Issue #1617 (Closed): Assoc array adds C++11 in the codebase
The associative arrays commit has broken Travis:
https://github.com/verilator/verilator/commit/b81295230a866e38c4183...
Todd Strader

12/01/2019

10:20 PM Issue #1614 (Resolved): Multiple label redefinition/parsing issue for constant functions used in ...
Fixed in git towards eventual 4.024 release.
Wilson Snyder
05:43 PM Issue #1615 (Closed): --output-split units documented as bytes, but appears to be closer to lines
Fixed in git.
Wilson Snyder
05:36 PM Issue #545 (Resolved): Support queues
Initial queue support (using method notation, not {} notation) is in git towards eventual 4.024 release.
Wilson Snyder
04:54 PM Issue #544 (Resolved): Support associative arrays
Associative array support for general types, excluding [*] and pattern assignment, is in git for eventual 4.024 relea... Wilson Snyder
04:01 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
Sorry, missed that, looks fine.
Wilson Snyder
01:02 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
m_foundTop is already in the constructor initializer list. Is it fine there or should I move it to the constructor's... Todd Strader
10:58 AM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
Todd, thanks for fixing. Feel free to push, you just need to init m_foundTop = false in the constructor.
Wilson Snyder

11/30/2019

04:37 PM Issue #1616 (Confirmed): Intenal Error of "Multiple root modules" happens if one of sub modules i...
That check was overly aggressive when inlining. Here's my proposed solution:
https://github.com/toddstrader/verilat...
Todd Strader

11/29/2019

11:21 PM Issue #1616: Intenal Error of "Multiple root modules" happens if one of sub modules is not inline...
Thanks for the example. I'll take a look. Todd Strader
10:43 PM Issue #1616 (Closed): Intenal Error of "Multiple root modules" happens if one of sub modules is n...
First of all, thank you very much for maintaining and evolving the great software.
I am exploring --protect-lib to...
Yutetsu TAKATSUKASA
08:13 PM Issue #1595: Fix interface reference tracing
Yeah, I'll just need some C str functions in the generated code to concatenate the two parts of the name. I'll do th... Todd Strader
07:20 PM Issue #1595: Fix interface reference tracing
I don't understand the need to change the include/ headers. I would think calling these decl functions with the prope... Wilson Snyder
05:14 PM Issue #1595: Fix interface reference tracing
What I've ended up on is creating a new AstIntfRef which is a child of AstCell nodes which are interfaces. These alw... Todd Strader

11/27/2019

02:07 PM Issue #1369: Raise error / warning on continous assignment to reg
Warning about assigning to output reg does not work for me. I'm using tag 4.022 without success.... Peter Gerst
11:12 AM Issue #1615 (Confirmed): --output-split units documented as bytes, but appears to be closer to lines
Thanks, will update these in the docs.
Output-split is roughly number of statements.
Wilson Snyder
10:58 AM Issue #1615: --output-split units documented as bytes, but appears to be closer to lines
It would also be worth mentioning that VM_PARALLEL_BUILDS needs to be set to 1 on the make command line to exploit pa... Julien Margetts
10:29 AM Issue #1615 (Closed): --output-split units documented as bytes, but appears to be closer to lines
The manual states the units of the --output-split option as bytes in both the summary and the full description, but i... Julien Margetts

11/26/2019

06:44 PM Issue #1614 (Confirmed): Multiple label redefinition/parsing issue for constant functions used in...
Will take a look.
You might also be able to work around it by replacing the return with "min=..."
Wilson Snyder

11/25/2019

03:24 PM Issue #1614 (Closed): Multiple label redefinition/parsing issue for constant functions used in co...
Minimal case below... Mitch Hayenga

11/23/2019

01:31 AM Issue #1572: Extend --protect-lib for foreign/embedded module use
For those looking to try embedding without protection, for just for experimentation, use a recent git version and try... Wilson Snyder

11/22/2019

11:13 PM Issue #1613 (Confirmed): verilator %Warning-WIDTH false positive
You're right, an easy cross check:
$display("%d", $size(o_dec_table.dec_len));
16
What looks to be...
Wilson Snyder
08:35 PM Issue #1613: verilator %Warning-WIDTH false positive
I think what I said above is consistent with IEEE 1800-2017 7.4.5 which says (among other things), "A subarray is an ... Tim Allen
07:44 PM Issue #1613: verilator %Warning-WIDTH false positive
does ... Tim Allen
05:21 PM Issue #1613: verilator %Warning-WIDTH false positive
The rightmost index of dec_len is 31:0, meaning it needs 6 bits to index into. Your cur_bit_len as you indicate is on... Wilson Snyder
03:28 PM Issue #1613 (Confirmed): verilator %Warning-WIDTH false positive
excerpt of file.sv...... Tim Allen
08:35 PM Issue #1612 (Closed): New VPI tests failing clang and Trusty builds
Cron seems happy now:
https://travis-ci.com/verilator/verilator/builds/137738748
Todd Strader

11/21/2019

11:43 PM Issue #1612 (Confirmed): New VPI tests failing clang and Trusty builds
Fixed, had uninit variable. Leaving open for now to see if Travis is happy.
Also added an error when test core du...
Wilson Snyder
12:57 PM Issue #1612 (Closed): New VPI tests failing clang and Trusty builds
Appears similar to bug1611. See:
https://travis-ci.com/verilator/verilator/builds/137544069
Affects --vlt and --...
Todd Strader

11/20/2019

11:49 PM Issue #1609 (Feature): Detect and warn appripriately on intentional latches
Wilson Snyder
11:48 PM Issue #1609 (Assigned): Detect and warn appripriately on intentional latches
Great, would be awesome to get this in.
The sensitivity list will at that point have some elements with combo on i...
Wilson Snyder
01:57 PM Issue #1609: Detect and warn appripriately on intentional latches
To ignore intentional standalone latches I think I need to update class ActiveDlyVisitor to supress the warning if th... Julien Margetts
03:36 AM Issue #1609: Detect and warn appripriately on intentional latches
Not sure I'm interpreting the question correctly, but...
Verilator doesn't presently identify self-identify latche...
Wilson Snyder
11:58 AM Issue #1611 (Closed): New VPI tests failing under --vltmt
Thanks, worked for me as builds went in different order, but should have noticed that code.
Fix pushed.
Wilson Snyder
10:40 AM Issue #1611 (Closed): New VPI tests failing under --vltmt
Two tests from this PR are failing CI under --vltmt:
https://github.com/verilator/verilator/pull/5
See:
https://...
Todd Strader
03:21 AM Issue #1595: Fix interface reference tracing
You can't have cells point to varscopes as it's a many-to-one arrangement, which is why scopes exist in the first pla... Wilson Snyder
12:24 AM Issue #1608 (Resolved): Strange dotted expression makes Verilator hang, but print correct error m...
Thanks for the report.
Fixed in git towards eventual 4.024 release.
Wilson Snyder

11/19/2019

03:30 PM Issue #1609 (Feature): Detect and warn appripriately on intentional latches
According to Cummings:
"Guideline #2: When modeling latches, use nonblocking assignments."
However, as I'm sure y...
Julien Margetts
12:39 PM Issue #1595: Fix interface reference tracing
I'm now thinking that the cleaner way to do this is to TraceDecl the entire interface. That way we can emit a TraceD... Todd Strader
10:37 AM Issue #1608 (Closed): Strange dotted expression makes Verilator hang, but print correct error mes...
The following module makes Verilator hang... Bogdan Vukobratovic
03:11 AM Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
Wilson Snyder

11/18/2019

10:04 AM Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
A pull is out against GTKwave. Once this completes:
- Move personal script to compare GTKwave include upstream to ...
Wilson Snyder

11/17/2019

06:39 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of...
Aimless Ramble
11:42 AM Issue #1605: for loop initialisation clause skipped
Thanks for fixing it so quickly. Andrew Holme
11:36 AM Issue #1604: Unknown node in split color() map on empty if
Thanks for fixing it. I had not attached any significance to them being unused; however, there are three instances o... Andrew Holme
09:58 AM Issue #1606 (Assigned): Complete string methods (starter project)
Implement the built-in string methods that are remaining:
- atobin, atohex, atoi, atooct, atoreal: Become a scanf....
Wilson Snyder

11/16/2019

10:24 PM Issue #1604 (Resolved): Unknown node in split color() map on empty if
Thanks for the good test case.
This was caused by your outputs (rx & ry) never being used, not sure if you noticed...
Wilson Snyder
08:18 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of the bits that are speci... Wilson Snyder
07:25 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> >But it doesn't capture internal behavioral source/destination
>
> It does, for example s...
Aimless Ramble

11/15/2019

11:38 PM Issue #1604 (Confirmed): Unknown node in split color() map on empty if
Will require some research. The irony is the point of the broken optimization is to transform it into exactly what y... Wilson Snyder
10:35 PM Issue #1604 (Closed): Unknown node in split color() map on empty if
... Andrew Holme
11:25 PM Issue #1605 (Resolved): for loop initialisation clause skipped
Sorry, that's nasty and should have been caught earlier, so fixing immediately.
FWIW "for (i=1; 0; )" was tested, ...
Wilson Snyder
10:47 PM Issue #1605 (Closed): for loop initialisation clause skipped
The body of the first for loop in this code never executes because the condition clause is always false; however it s... Andrew Holme
08:48 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
>But it doesn't capture internal behavioral source/destination
It does, for example see the varref (references to...
Wilson Snyder
08:41 PM Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> Verilog-perl has some of this information, but from what you describe I would suggest first l...
Aimless Ramble
09:36 AM Issue #1598: Problems attempting to redefine VL_PRINTF
Thanks for the pointers, I will persevere with that aproach and try and get a patch out ... Julien Margetts
08:39 AM Issue #1598 (Confirmed): Problems attempting to redefine VL_PRINTF
Originally VL_PRINTF was intended to be overridden in a .mk file which overrode the default verilator.mk file. For t... Wilson Snyder
09:08 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
This is to protect against what in some cases may become:
int foo;
void foo();
which causes a mess of course. ...
Wilson Snyder
02:11 AM Issue #1603: Statement label should be allowed to be a duplicate of a parameter
Ok well that formatting failed - trying again:
This syntax is not allowed by verilator:...
Pieter Kapsenberg
02:09 AM Issue #1603 (WillNotFix): Statement label should be allowed to be a duplicate of a parameter
This syntax is not allowed by verilator:... Pieter Kapsenberg
08:02 AM Issue #1595 (Assigned): Fix interface reference tracing
Wilson Snyder
08:02 AM Issue #1602 (Assigned): Investigate Travis CMake error message
Wilson Snyder
08:01 AM Issue #1601 (Confirmed): Add SystemC to Travis
Hopefully someone has a pre-built package otherwise we'll need to build it, as too slow/unstable to build every time.... Wilson Snyder
07:59 AM Issue #1600 (Confirmed): Add vcddiff to Travis
Wilson Snyder
07:59 AM Issue #1600: Add vcddiff to Travis
Might want to put a binary somewhere as this almost never changes.
Wilson Snyder

11/14/2019

11:09 PM Issue #1602 (Assigned): Investigate Travis CMake error message
I've only seen this in Travis (and maybe only with Trusty). It was showing up in the logs because of a probably unre... Todd Strader
11:06 PM Issue #1601 (Confirmed): Add SystemC to Travis
SystemC tests are being skipped right now. Todd Strader
11:05 PM Issue #1600 (Closed): Add vcddiff to Travis
A number of tests are not running because this is missing. Todd Strader
11:04 PM Issue #1596 (Resolved): Travis tweaks
Squashed and pushed to both repos. I added some Makefile logic to examples/xml_py to skip the example if Python < 3.... Todd Strader
09:04 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
Verilog-perl has some of this information, but from what you describe I would suggest first looking at Verilator's --... Wilson Snyder
06:40 PM Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
I have trying to form a signal connectivity Parser within a Module file. It Can read (one or multiple) Verilog files ... Aimless Ramble
03:27 PM Issue #1598 (Closed): Problems attempting to redefine VL_PRINTF
I need my verilated model to call something other than printf to perform output $display, and the intended way to do ... Julien Margetts
 

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