From 12/20/2018 to 01/18/2019
- Is it possible that @VM_USER_DIR@ is being defined/used incorrectly in _Verilator_-generated makefiles?<br>
- 10:55 PM Development: RE: interface modport expression
- I would like to 2nd this motion.
Modports Expressions, let alone Modports, aren't particularly common. But the pro...
- 12:24 AM Usage: RE: Several questions, re: the `--inline-mult` option.
- 1. An internal ast node E.g. add.
2. Right, will fix.
3. It has been used on larger designs however gcc has bee...
- 12:03 AM Usage: RE: Can I call out to a foreign language module, via VPI, from a Verilog submodule?
- Not easily, I think you are looking for something like this:
- 11:47 PM Usage: RE: What's a good value to give the --output-split-cfuncs flag?
- Maybe start with 50000, see how long it takes, and adjust to get e.g. 5 minute gcc per c++ file.
- Any advice on what value to give in the @--output-split-cfuncs@ flag?
- In thinking about how to work around this limitation whereby we're unable to use pre-Verilated *.o files to provide V...
- I have some questions, re: the @--inline-mult@ option, that I hoped someone might know the answers to:
# What is a...
- 02:05 AM Usage: RE: Best practice for compiling top-level test bench and linking final executable, when NO...
- --exe shouldn't be slowing anything down, it just adds a make rule, you can put your .cpp's on the command line and u...
- My design is so big (2 hour _Verilator_ translation/compilation time) that I'm not using the @--exe@ option.<br>
- 10:32 PM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
- D'oh! Sorry, just me being stupid.<br>
I forgot to refresh an Emacs buffer.<br>
Thanks very much for your time, and...
- 06:46 PM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
- It does seem inconsistent. If you delete your vrltr_out and rebuild is it OK?
- 06:09 PM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
- Thanks, Wilson!
Does the @-DVL_THREADED@ flag get put in the @V<blkname>_classes.mk@ file?
I'm looking in that fi...
- 02:25 AM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
- I think you aren't passing in the flags that verilator puts into the generated makefile, specifically -DVL_THREADED
- I just started trying to use multi-threading and am getting this error, when attempting to compile my top-level C++ t...
- 01:49 PM Usage: RE: Building Verilator to work with multiple C++ compilers
- In general, except for compile options Verilated code is designed to work on any target compiler (i.e. output code do...
- When building Verilator, the configure script discovers options for the target C++ compiler and writes them into VERI...
- 01:40 PM Usage: RE: Using packed struct for register definition
Ok I understand. Coming from vhdl I try to get familiar with Verilog and Verilator. Will try to get info from other...
- 12:57 PM Usage: RE: Using packed struct for register definition
- reg is a datatype just like 'FP'. However please note this site is intended to discuss Verilator and other related f...
- Verilator supports ...
- 10:31 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
- 09:20 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
- Use the DPI.
import "DPI-C" pure function void send_byte(uint8_t b);
always @ (posedge clk) begin
- 09:17 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
- I looking at a way where I can emulate peripherals via C functions
and was reading through https://zipcpu.com/blog/...
- 07:44 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
- Verilator keeps, adds or combines classes based on a bunch of algorithms attempting to maximize performance. For the ...
- A Verilator newbee question:
When I specify a hirarchical verilog design with multiple modules, split in several fil...
- 12:43 PM Development: RE: Multiple top modules for lint
- I didn't patch the codes inside for it.
A temporary wrapper file is made outside of verilator and thrown with origin...
- 12:24 PM Development: RE: Multiple top modules for lint
- Nice. Can you post the contributed patches back (including some test cases) please? Thanks
- 12:20 PM Development: RE: Multiple top modules for lint
- I've done. Thanks again.
- 11:37 AM Usage: RE: Verilate SystemVerilog RTL without a top module?
- So the problem is you want to verilate something at top with interfaces poking out the top?
Typically when doing t...
- I'm a new to using verilator and I am trying to use it to cross verify RTL with an architectural model. Our model is ...
- 11:22 PM Usage: RE: Any way around: %Error-ASSIGNIN, w/o editing Verilog?
- ASSIGNIN can be disabled just like a warning, using e.g. //verilator pragmas, vlt files, or command line - see the ma...
- I'm bumping into this error: @%Error-ASSIGNIN@, because some behavioral simulation libraries provided to me by my fou...
- 11:10 PM Usage: RE: Compile errors with Mingw32 on fstapi.c
- Can you create a patch to fix these, then send the result to "Tony Bybell" <email@example.com> so they can be fix...
- 12:26 PM Development: RE: Multiple top modules for lint
- It is good idea to use a top wrapper. I'll have to try it.
- 11:02 AM Development: RE: Multiple top modules for lint
- P.S. Looping in main() would be a mess and cause other problems. Looping outside by calling verilator many times is ...
- 11:01 AM Development: RE: Multiple top modules for lint
Probably the easiest fix would be to inside the generated top wrapper instead instantiate every module found ...
- 10:51 AM Development: RE: Multiple top modules for lint
- But it is possible to call separately like this ......
- 09:56 AM Development: RE: Multiple top modules for lint
- At present there must be a single top module, multiple ones are not supported even in lint-only.
Or if I misunders...
How can I easily modify codes to repeat multiple modules for --lint-only mode ?
Instead of repeating outside ...
- 12:19 PM Usage: RE: How to use SystemVerilog package syntax?
- I understand it's not a friendly message, but unfortunately comes from bison not Verilator sources so isn't really ch...
- 06:11 AM Usage: RE: No "#pragma omp ..." lines in generated C++ code when using `--threads 2`?
- Verilator uses C++11 threads instead.
- I just tried the _--threads_ option: @--threads 2@. <br>
I was expecting to see some lines of the form:...
- 03:39 PM Usage: RE: Wait on rising edge from c++
- Actually, there is only one first if() for clock signal per circuit and only waiting simulation processes for this cl...
- 04:02 PM Usage: RE: How to use SystemVerilog package syntax?
- Sorry, this was a red herring.
The problem was that the class I was attempting to access hadn’t been defined, yet.
- 04:33 AM Usage: RE: How to use SystemVerilog package syntax?
- Er, what is the code it is complaining about?
- I'm having trouble using basic SystemVerilog package syntax.
I'm getting this error:...
- 11:54 AM Usage: RE: Wait on rising edge from c++
- I suspect it will have trouble with larger designs where multiple if()'s are inserted, but give it a try.
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