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Activity

From 12/20/2018 to 01/18/2019

Today

04:02 PM Usage: Is VM_USER_DIR defined incorrectly in Verilator-generated makefiles?
Is it possible that @VM_USER_DIR@ is being defined/used incorrectly in _Verilator_-generated makefiles?<br>
That is,...
David Banas

01/16/2019

10:55 PM Development: RE: interface modport expression
I would like to 2nd this motion.
Modports Expressions, let alone Modports, aren't particularly common. But the pro...
Bob Kitchin
12:24 AM Usage: RE: Several questions, re: the `--inline-mult` option.
1. An internal ast node E.g. add.
2. Right, will fix.
3. It has been used on larger designs however gcc has bee...
Wilson Snyder
12:03 AM Usage: RE: Can I call out to a foreign language module, via VPI, from a Verilog submodule?
Not easily, I think you are looking for something like this:
https://www.veripool.org/boards/3/topics/2348-Verilat...
Wilson Snyder

01/15/2019

11:47 PM Usage: RE: What's a good value to give the --output-split-cfuncs flag?
Maybe start with 50000, see how long it takes, and adjust to get e.g. 5 minute gcc per c++ file. Wilson Snyder
08:41 PM Usage: What's a good value to give the --output-split-cfuncs flag?
Any advice on what value to give in the @--output-split-cfuncs@ flag?
Thanks,
-db
David Banas
09:30 PM Usage: Can I call out to a foreign language module, via VPI, from a Verilog submodule?
In thinking about how to work around this limitation whereby we're unable to use pre-Verilated *.o files to provide V... David Banas
12:54 AM Usage: Several questions, re: the `--inline-mult` option.
I have some questions, re: the @--inline-mult@ option, that I hoped someone might know the answers to:
# What is a...
David Banas

01/14/2019

02:05 AM Usage: RE: Best practice for compiling top-level test bench and linking final executable, when NO...
--exe shouldn't be slowing anything down, it just adds a make rule, you can put your .cpp's on the command line and u... Wilson Snyder

01/12/2019

10:40 PM Usage: Best practice for compiling top-level test bench and linking final executable, when NOT us...
My design is so big (2 hour _Verilator_ translation/compilation time) that I'm not using the @--exe@ option.<br>
How...
David Banas
10:32 PM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
D'oh! Sorry, just me being stupid.<br>
I forgot to refresh an Emacs buffer.<br>
Thanks very much for your time, and...
David Banas
06:46 PM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
It does seem inconsistent. If you delete your vrltr_out and rebuild is it OK? Wilson Snyder
06:09 PM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
Thanks, Wilson!
Does the @-DVL_THREADED@ flag get put in the @V<blkname>_classes.mk@ file?
I'm looking in that fi...
David Banas
02:25 AM Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
I think you aren't passing in the flags that verilator puts into the generated makefile, specifically -DVL_THREADED Wilson Snyder
12:32 AM Usage: error: 'VL_CPU_RELAX' was not declared in this scope.
I just started trying to use multi-threading and am getting this error, when attempting to compile my top-level C++ t... David Banas

01/08/2019

01:49 PM Usage: RE: Building Verilator to work with multiple C++ compilers
In general, except for compile options Verilated code is designed to work on any target compiler (i.e. output code do... Wilson Snyder
12:21 PM Usage: Building Verilator to work with multiple C++ compilers
When building Verilator, the configure script discovers options for the target C++ compiler and writes them into VERI... Al Grant

01/07/2019

01:40 PM Usage: RE: Using packed struct for register definition

Ok I understand. Coming from vhdl I try to get familiar with Verilog and Verilator. Will try to get info from other...
Konrad Eisele
12:57 PM Usage: RE: Using packed struct for register definition
reg is a datatype just like 'FP'. However please note this site is intended to discuss Verilator and other related f... Wilson Snyder
12:07 PM Usage: Using packed struct for register definition
Verilator supports ... Konrad Eisele

01/06/2019

10:31 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
Thanks Konrad Eisele
09:20 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
Use the DPI.
import "DPI-C" pure function void send_byte(uint8_t b);
always @ (posedge clk) begin
if...
Wilson Snyder
09:17 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
I looking at a way where I can emulate peripherals via C functions
and was reading through https://zipcpu.com/blog/...
Konrad Eisele
07:44 PM Usage: RE: Retain verilog hirarchy in c++ class hirarchy ?
Verilator keeps, adds or combines classes based on a bunch of algorithms attempting to maximize performance. For the ... Wilson Snyder
04:39 PM Usage: Retain verilog hirarchy in c++ class hirarchy ?
A Verilator newbee question:
When I specify a hirarchical verilog design with multiple modules, split in several fil...
Konrad Eisele

01/05/2019

12:43 PM Development: RE: Multiple top modules for lint
I didn't patch the codes inside for it.
A temporary wrapper file is made outside of verilator and thrown with origin...
Kris Jeon
12:24 PM Development: RE: Multiple top modules for lint
Nice. Can you post the contributed patches back (including some test cases) please? Thanks Wilson Snyder
12:20 PM Development: RE: Multiple top modules for lint
I've done. Thanks again.
!https://raw.githubusercontent.com/poucotm/Links/master/image/SublimeLinter-Contrib-Veril...
Kris Jeon
11:37 AM Usage: RE: Verilate SystemVerilog RTL without a top module?
So the problem is you want to verilate something at top with interfaces poking out the top?
Typically when doing t...
Wilson Snyder

01/04/2019

06:51 PM Usage: Verilate SystemVerilog RTL without a top module?
I'm a new to using verilator and I am trying to use it to cross verify RTL with an architectural model. Our model is ... Justin Jones

01/03/2019

11:22 PM Usage: RE: Any way around: %Error-ASSIGNIN, w/o editing Verilog?
ASSIGNIN can be disabled just like a warning, using e.g. //verilator pragmas, vlt files, or command line - see the ma... Wilson Snyder
10:17 PM Usage: Any way around: %Error-ASSIGNIN, w/o editing Verilog?
I'm bumping into this error: @%Error-ASSIGNIN@, because some behavioral simulation libraries provided to me by my fou... David Banas

01/02/2019

11:10 PM Usage: RE: Compile errors with Mingw32 on fstapi.c
Can you create a patch to fix these, then send the result to "Tony Bybell" <bybell@rocketmail.com> so they can be fix... Wilson Snyder
12:26 PM Development: RE: Multiple top modules for lint
It is good idea to use a top wrapper. I'll have to try it.
Thanks!
Kris Jeon
11:02 AM Development: RE: Multiple top modules for lint
P.S. Looping in main() would be a mess and cause other problems. Looping outside by calling verilator many times is ... Wilson Snyder
11:01 AM Development: RE: Multiple top modules for lint
Yes.
Probably the easiest fix would be to inside the generated top wrapper instead instantiate every module found ...
Wilson Snyder
10:51 AM Development: RE: Multiple top modules for lint
But it is possible to call separately like this ...... Kris Jeon
09:56 AM Development: RE: Multiple top modules for lint
At present there must be a single top module, multiple ones are not supported even in lint-only.
Or if I misunders...
Wilson Snyder
09:48 AM Development: Multiple top modules for lint
Hi,
How can I easily modify codes to repeat multiple modules for --lint-only mode ?
Instead of repeating outside ...
Kris Jeon
12:19 PM Usage: RE: How to use SystemVerilog package syntax?
I understand it's not a friendly message, but unfortunately comes from bison not Verilator sources so isn't really ch... Wilson Snyder

01/01/2019

06:11 AM Usage: RE: No "#pragma omp ..." lines in generated C++ code when using `--threads 2`?
Verilator uses C++11 threads instead. Wilson Snyder
12:59 AM Usage: No "#pragma omp ..." lines in generated C++ code when using `--threads 2`?
I just tried the _--threads_ option: @--threads 2@. <br>
I was expecting to see some lines of the form:...
David Banas

12/30/2018

03:39 PM Usage: RE: Wait on rising edge from c++
Actually, there is only one first if() for clock signal per circuit and only waiting simulation processes for this cl... Michal Orsak

12/26/2018

04:02 PM Usage: RE: How to use SystemVerilog package syntax?
Sorry, this was a red herring.
The problem was that the class I was attempting to access hadn’t been defined, yet.
...
David Banas
04:33 AM Usage: RE: How to use SystemVerilog package syntax?
Er, what is the code it is complaining about? Wilson Snyder

12/25/2018

06:07 PM Usage: How to use SystemVerilog package syntax?
I'm having trouble using basic SystemVerilog package syntax.
I'm getting this error:...
David Banas

12/20/2018

11:54 AM Usage: RE: Wait on rising edge from c++
I suspect it will have trouble with larger designs where multiple if()'s are inserted, but give it a try.
Wilson Snyder
 

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