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Activity

From 11/14/2019 to 12/13/2019

12/11/2019

10:08 PM Usage: RE: Verilog 2001 config as an alternate to using non standard `uselib
I don't think config is widely supported, we'll look at adding `uselib.
Wilson Snyder
08:37 PM Usage: Verilog 2001 config as an alternate to using non standard `uselib

In verilog I only know of 2 methods to deal with the problem of multiple modules with same name in different librar...
Frederic Antonin
11:56 AM Usage: RE: it is any possible to make verilator case-insensitive ?
Verilog is a case sensitive language, so I'm reluctant to add such an option as it would encourage standard violation... Wilson Snyder
06:09 AM Usage: it is any possible to make verilator case-insensitive ?
For some reason,I use the uppercase letters as module name,like ABC,but its file named abc.v.
But it seems that veri...
Jacob Liang

12/03/2019

08:34 AM Usage: RE: Correct usage of enumerated type methods
Thanks for the quick fix.
We are just starting development with SV and V at our company but it looks like that an ...
Tobias Rosenkranz

12/02/2019

11:58 PM Usage: RE: Correct usage of enumerated type methods
This was a false message. I just pushed a change to git to fix this towards eventual 4.024 release.
Wilson Snyder
03:24 PM Usage: Correct usage of enumerated type methods
Hello everyone,
I have a problem with enumerated type methods. I always get an ...
Tobias Rosenkranz
11:04 AM Development: RE: question of development
Love to have whatever contributions/assistance you are willing to provide.
Please check out the git tree and see t...
Wilson Snyder
03:54 AM Development: question of development
We are interested in participating in tool development and would like to learn more about it.
Is there any document ...
Marshal qiao
02:23 AM Usage: RE: Very basic eval() usage question
The code snippet I pasted above actually works fine. There was something in my actual app which didn't work, for some... Julius Baxter

11/27/2019

06:25 AM Usage: RE: Trouble simulating altera-generated floating point units
It's a fundamental problem, try rewriting. Wilson Snyder
02:31 AM Usage: RE: Trouble simulating altera-generated floating point units
Is this problem fundamentally due to verilator being a cycle simulator instead of an event simulator? Will it be poss... Evan Andersen

11/24/2019

07:32 PM Usage: RE: Trouble simulating altera-generated floating point units
Hmm, I don't think it's related to that. I just used 'x' as a variable name in my previous code example. There is alr... Evan Andersen
01:40 PM Usage: RE: Trouble simulating altera-generated floating point units
You could try the --x-initial-edge flag. Or, add an initial statement. Wilson Snyder
08:35 AM Usage: RE: Trouble simulating altera-generated floating point units
Ok, I have figured out the issue, but I am unsure how to solve it. Inside the altera memory sim libraries, there is c... Evan Andersen

11/23/2019

01:29 AM Usage: RE: Any chance to use Verilator together with Icuras?
Great! There's been a lot of progress in the last month or so, with --protect-lib added etc, please see bug1572. I'... Wilson Snyder
12:44 AM Usage: RE: Any chance to use Verilator together with Icuras?
... "Verilator has plans to add "embedding" of a model in another simulator"
This is exactly how I use Verilator w...
Julien Margetts

11/22/2019

11:21 AM Usage: RE: Trouble simulating altera-generated floating point units
Glad you're giving Verilator a try. It's most likely something simple, perhaps with a hint buried in a warning as yo... Wilson Snyder
07:00 AM Usage: Trouble simulating altera-generated floating point units
It is my first time using verilator. I wrote a simple program to test the floating point units generated by altera's ... Evan Andersen

11/19/2019

03:06 AM Usage: RE: Basic questions: Multiple modules and using "#"
1) Yes, you can put multiple modules per file.
2) You'd write this in C code, for example in = 0; then make time p...
Wilson Snyder

11/18/2019

09:01 PM Usage: Basic questions: Multiple modules and using "#"
Hello,
I want to play with some simple modules and signals and tried this:...
Patrick Mulder
 

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