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Usage

Help on using Verilator

Subject Author Created Replies Last message
Is VM_USER_DIR defined incorrectly in Verilator-generated makefiles? David Banas 01/18/2019 04:02 PM 0
Several questions, re: the `--inline-mult` option. David Banas 01/15/2019 12:54 AM 1 Added by Wilson Snyder 3 days ago
RE: Several questions, re: the `--inline-mult` option.
Can I call out to a foreign language module, via VPI, from a Verilog submodule? David Banas 01/15/2019 09:30 PM 1 Added by Wilson Snyder 3 days ago
RE: Can I call out to a foreign language module, via VPI,...
What's a good value to give the --output-split-cfuncs flag? David Banas 01/15/2019 08:41 PM 1 Added by Wilson Snyder 3 days ago
RE: What's a good value to give the --output-split-cfuncs...
Best practice for compiling top-level test bench and linking final executable, when NOT using the '--exe' option? David Banas 01/12/2019 10:40 PM 1 Added by Wilson Snyder 5 days ago
RE: Best practice for compiling top-level test bench and ...
error: 'VL_CPU_RELAX' was not declared in this scope. David Banas 01/12/2019 12:32 AM 4 Added by David Banas 6 days ago
RE: error: 'VL_CPU_RELAX' was not declared in this scope.
Building Verilator to work with multiple C++ compilers Al Grant 01/08/2019 12:21 PM 1 Added by Wilson Snyder 10 days ago
RE: Building Verilator to work with multiple C++ compilers
Using packed struct for register definition Konrad Eisele 01/07/2019 12:07 PM 2 Added by Konrad Eisele 11 days ago
RE: Using packed struct for register definition
Retain verilog hirarchy in c++ class hirarchy ? Konrad Eisele 01/06/2019 04:39 PM 4 Added by Konrad Eisele 12 days ago
RE: Retain verilog hirarchy in c++ class hirarchy ?
Verilate SystemVerilog RTL without a top module? Justin Jones 01/04/2019 06:51 PM 1 Added by Wilson Snyder 13 days ago
RE: Verilate SystemVerilog RTL without a top module?
Any way around: %Error-ASSIGNIN, w/o editing Verilog? David Banas 01/03/2019 10:17 PM 1 Added by Wilson Snyder 15 days ago
RE: Any way around: %Error-ASSIGNIN, w/o editing Verilog?
Compile errors with Mingw32 on fstapi.c Richard Myers 12/19/2018 02:48 AM 1 Added by Wilson Snyder 16 days ago
RE: Compile errors with Mingw32 on fstapi.c
How to use SystemVerilog package syntax? David Banas 12/25/2018 06:07 PM 3 Added by Wilson Snyder 16 days ago
RE: How to use SystemVerilog package syntax?
No "#pragma omp ..." lines in generated C++ code when using `--threads 2`? David Banas 01/01/2019 12:59 AM 1 Added by Wilson Snyder 17 days ago
RE: No "#pragma omp ..." lines in generated C++ code when...
Wait on rising edge from c++ Michal Orsak 12/02/2018 01:30 AM 11 Added by Michal Orsak 19 days ago
RE: Wait on rising edge from c++
Set timescale in model at runtime (ie. before first eval())? Richard Myers 12/17/2018 01:24 AM 4 Added by Wilson Snyder about 1 month ago
RE: Set timescale in model at runtime (ie. before first e...
$readmemh should apply relative paths to verilog file (not to verilator running folder) Jose Tejada 12/08/2018 08:28 AM 1 Added by Wilson Snyder about 1 month ago
RE: $readmemh should apply relative paths to verilog file...
lxt2_config.h problem. HyungKi Jeong 10/02/2018 05:34 AM 6 Added by Wilson Snyder about 1 month ago
RE: lxt2_config.h problem.
threaded compile error message David Stanford 11/14/2018 06:02 PM 7 Added by Wilson Snyder 2 months ago
RE: threaded compile error message
Getting a list of module and SystemVerilog interface dependencies Hayden Roche 10/23/2018 05:18 PM 14 Added by Wilson Snyder 3 months ago
RE: Getting a list of module and SystemVerilog interface ...
bug in fst_config.h HyungKi Jeong 10/30/2018 10:32 AM 3 Added by HyungKi Jeong 3 months ago
RE: bug in fst_config.h
make program fault with MinGW on v4.006 HyungKi Jeong 10/30/2018 10:46 AM 0
Multiple comma-separated declaration in one for-loop Yu Sheng Lin 10/17/2018 01:02 PM 1 Added by Wilson Snyder 3 months ago
RE: Multiple comma-separated declaration in one for-loop
multiple -CFLAGS Iztok Jeras 10/10/2018 08:43 PM 2 Added by Iztok Jeras 3 months ago
RE: multiple -CFLAGS
Needs base class of 'VerilatedLxt2C', 'VerilatedVcdC' and 'VerilatedFstC' HyungKi Jeong 10/11/2018 05:11 AM 1 Added by Wilson Snyder 3 months ago
RE: Needs base class of 'VerilatedLxt2C', 'VerilatedVcdC'...
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