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Usage

Help on using Verilator

Subject Author Created Replies Last message
Simulation slow down due to a large new block that's idle Stan Sokorac 03/08/2019 02:49 PM 1 Added by Wilson Snyder 11 days ago
RE: Simulation slow down due to a large new block that's ...
Trouble getting started with linting Charles Eddleston 03/07/2019 05:11 AM 2 Added by Charles Eddleston 13 days ago
RE: Trouble getting started with linting
FST dumping 100x slower than VCD Stan Sokorac 01/25/2019 03:16 PM 4 Added by Jérémie Chabloz 14 days ago
RE: FST dumping 100x slower than VCD
error using verilatedvcdsc divyakumar shah 03/06/2019 03:25 PM 0
Multiple comma-separated declaration in one for-loop Yu Sheng Lin 10/17/2018 01:02 PM 6 Added by Yu Sheng Lin 17 days ago
RE: Multiple comma-separated declaration in one for-loop
How to show enum names in gtkwave? Soya Ohnishi 02/26/2019 03:42 AM 4 Added by Soya Ohnishi 21 days ago
RE: How to show enum names in gtkwave?
About assigning values to C++ models and getting values(VPI) Yu Kai Liang 02/26/2019 12:10 PM 9 Added by Wilson Snyder 22 days ago
RE: About assigning values to C++ models and getting valu...
Why does my module I/O signature change, even when I give the /* verilator no_inline_module */ directive? David Banas 02/20/2019 12:44 AM 2 Added by David Banas 28 days ago
RE: Why does my module I/O signature change, even when I ...
Why is my generated archive file so huge? David Banas 02/08/2019 07:20 PM 25 Added by Wilson Snyder 28 days ago
RE: Why is my generated archive file so huge?
Verilator + SWIG = Python wrapper? Chase Meadors 06/09/2014 04:39 AM 4 Added by Aaron Kelly 28 days ago
RE: Verilator + SWIG = Python wrapper?
"File truncated" error from ar when attempting to create V<my_block>__ALL.a ?! David Banas 02/08/2019 12:41 AM 4 Added by David Banas about 1 month ago
RE: "File truncated" error from ar when attempting to cre...
evaluating verilator John Coiner 07/18/2014 06:29 PM 4 Added by Wilson Snyder about 2 months ago
RE: evaluating verilator
How to pack arrays properly in my C++ test bench? David Banas 01/24/2019 01:43 AM 7 Added by Wilson Snyder about 2 months ago
RE: How to pack arrays properly in my C++ test bench?
Is VM_USER_DIR defined incorrectly in Verilator-generated makefiles? David Banas 01/18/2019 04:02 PM 1 Added by Wilson Snyder about 2 months ago
RE: Is VM_USER_DIR defined incorrectly in Verilator-gener...
Compile errors with Mingw32 on fstapi.c Richard Myers 12/19/2018 02:48 AM 2 Added by Wilson Snyder about 2 months ago
RE: Compile errors with Mingw32 on fstapi.c
Incremental verilate on large designs? Stan Sokorac 01/20/2019 02:54 PM 1 Added by Wilson Snyder about 2 months ago
RE: Incremental verilate on large designs?
Several questions, re: the `--inline-mult` option. David Banas 01/15/2019 12:54 AM 1 Added by Wilson Snyder 2 months ago
RE: Several questions, re: the `--inline-mult` option.
Can I call out to a foreign language module, via VPI, from a Verilog submodule? David Banas 01/15/2019 09:30 PM 1 Added by Wilson Snyder 2 months ago
RE: Can I call out to a foreign language module, via VPI,...
What's a good value to give the --output-split-cfuncs flag? David Banas 01/15/2019 08:41 PM 1 Added by Wilson Snyder 2 months ago
RE: What's a good value to give the --output-split-cfuncs...
Best practice for compiling top-level test bench and linking final executable, when NOT using the '--exe' option? David Banas 01/12/2019 10:40 PM 1 Added by Wilson Snyder 2 months ago
RE: Best practice for compiling top-level test bench and ...
error: 'VL_CPU_RELAX' was not declared in this scope. David Banas 01/12/2019 12:32 AM 4 Added by David Banas 2 months ago
RE: error: 'VL_CPU_RELAX' was not declared in this scope.
Building Verilator to work with multiple C++ compilers Al Grant 01/08/2019 12:21 PM 1 Added by Wilson Snyder 2 months ago
RE: Building Verilator to work with multiple C++ compilers
Using packed struct for register definition Konrad Eisele 01/07/2019 12:07 PM 2 Added by Konrad Eisele 2 months ago
RE: Using packed struct for register definition
Retain verilog hirarchy in c++ class hirarchy ? Konrad Eisele 01/06/2019 04:39 PM 4 Added by Konrad Eisele 2 months ago
RE: Retain verilog hirarchy in c++ class hirarchy ?
Verilate SystemVerilog RTL without a top module? Justin Jones 01/04/2019 06:51 PM 1 Added by Wilson Snyder 2 months ago
RE: Verilate SystemVerilog RTL without a top module?
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