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Usage

Help on using Verilator

Subject Author Created Replies Last message
Correct usage of enumerated type methods Tobias Rosenkranz 12/02/2019 03:24 PM 2 Added by Tobias Rosenkranz 8 days ago
RE: Correct usage of enumerated type methods
Very basic eval() usage question Julius Baxter 11/13/2019 03:31 AM 2 Added by Julius Baxter 9 days ago
RE: Very basic eval() usage question
Trouble simulating altera-generated floating point units Evan Andersen 11/22/2019 07:00 AM 6 Added by Wilson Snyder 14 days ago
RE: Trouble simulating altera-generated floating point units
Any chance to use Verilator together with Icuras? Yong Fu 06/26/2019 08:59 AM 3 Added by Wilson Snyder 18 days ago
RE: Any chance to use Verilator together with Icuras?
Basic questions: Multiple modules and using "#" Patrick Mulder 11/18/2019 09:01 PM 1 Added by Wilson Snyder 22 days ago
RE: Basic questions: Multiple modules and using "#"
Testbench patterns to run N cycles ? Patrick Mulder 11/02/2019 11:50 AM 1 Added by Wilson Snyder about 1 month ago
RE: Testbench patterns to run N cycles ?
Multiple comma-separated declaration in one for-loop Yu Sheng Lin 10/17/2018 01:02 PM 7 Added by Wilson Snyder about 1 month ago
RE: Multiple comma-separated declaration in one for-loop
Using vcs to simulate design with multiple verilated uC cores? Oleg Rodionov 09/10/2019 02:16 PM 9 Added by Todd Strader about 1 month ago
RE: Using vcs to simulate design with multiple verilated ...
verilator include alex al 10/23/2019 04:32 PM 1 Added by Wilson Snyder about 2 months ago
RE: verilator include
FST dumping 100x slower than VCD Stan Sokorac 01/25/2019 03:16 PM 8 Added by Wilson Snyder about 2 months ago
RE: FST dumping 100x slower than VCD
Reduce Compile Memory Kevin Hurd 06/28/2016 12:08 AM 4 Added by Kevin Hurd 2 months ago
RE: Reduce Compile Memory
recursive function support? Yong Fu 09/27/2019 08:51 AM 1 Added by Wilson Snyder 2 months ago
RE: recursive function support?
Workaround for unsupported fopen in verilog library Ted X 09/26/2019 09:30 PM 1 Added by Wilson Snyder 2 months ago
RE: Workaround for unsupported fopen in verilog library
Increasing performance in a moderately clock gated design James Connolly 08/15/2019 06:09 PM 5 Added by Wilson Snyder 3 months ago
RE: Increasing performance in a moderately clock gated de...
Error on 2D array of interface Ânderson Ignacio Da Silva 09/12/2019 01:19 PM 2 Added by Ânderson Ignacio Da Silva 3 months ago
RE: Error on 2D array of interface
any chance of gettting deassign working? Kurt Peters 05/24/2013 06:14 PM 3 Added by Wilson Snyder 3 months ago
RE: any chance of gettting deassign working?
Single-bit signals represented as VL_SIG8 Slava B 09/09/2019 10:19 AM 1 Added by Wilson Snyder 3 months ago
RE: Single-bit signals represented as VL_SIG8
Conversion of a hierarchical design Slava B 09/04/2019 11:51 AM 3 Added by Slava B 3 months ago
RE: Conversion of a hierarchical design
Verilator should have converted inout ports to input/output pairs. Slava B 09/03/2019 08:27 AM 2 Added by Slava B 3 months ago
RE: Verilator should have converted inout ports to input/...
Unsupported: wor Slava B 08/27/2019 08:13 AM 1 Added by Wilson Snyder 4 months ago
RE: Unsupported: wor
Incremental verilate on large designs? Stan Sokorac 01/20/2019 02:54 PM 3 Added by Wilson Snyder 4 months ago
RE: Incremental verilate on large designs?
A strange code generated from parametric module. Slava B 07/29/2019 06:32 AM 2 Added by Slava B 4 months ago
RE: A strange code generated from parametric module.
Error: verilator threw signal 2 Yifei He 07/27/2019 08:05 AM 1 Added by Wilson Snyder 5 months ago
RE: Error: verilator threw signal 2
How to disable MULTITOP? Ignatius Rivaldi 04/02/2019 06:54 AM 2 Added by Wilson Snyder 5 months ago
RE: How to disable MULTITOP?
use enum from a sv module in c++ testbench using /*verilator_public*/ toby matthews 07/07/2019 09:31 AM 2 Added by toby matthews 5 months ago
RE: use enum from a sv module in c++ testbench using /*ve...
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