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Development

Discussions related to Verilator internals and development

Subject Author Created Replies Last message
question of development Marshal qiao 12/02/2019 03:54 AM 1 Added by Wilson Snyder 8 days ago
RE: question of development
Anywhere to find the description of cycle based simulator Yong Fu 10/27/2019 07:22 AM 4 Added by Wilson Snyder about 1 month ago
RE: Anywhere to find the description of cycle based simul...
enhancement to support SystemVerilog for loop multiple vars Jon Stahl 10/28/2019 03:11 PM 1 Added by Wilson Snyder about 1 month ago
RE: enhancement to support SystemVerilog for loop multipl...
Adding foreign module support to Verilator Xavier Delacour 09/20/2017 01:24 AM 11 Added by Xavier Delacour about 2 months ago
RE: Adding foreign module support to Verilator
Requiring C++11 compiler Wilson Snyder 06/26/2018 11:17 AM 10 Added by Wilson Snyder about 2 months ago
RE: Requiring C++11 compiler
sc_inout and tristate support Mikael Strom 11/27/2015 09:38 AM 5 Added by Wilson Snyder 3 months ago
RE: sc_inout and tristate support
Building Verilator with Bazel Kevin Kiningham 09/18/2018 03:22 AM 23 Added by Kevin Kiningham 3 months ago
RE: Building Verilator with Bazel
Verilator fails to warn/error on procedural assignment to wire Neil Turton 01/01/2015 06:43 PM 7 Added by Wilson Snyder 4 months ago
RE: Verilator fails to warn/error on procedural assignmen...
RFC: DPI encapsulated Verilog instead of encryption Todd Strader 08/07/2019 11:04 AM 5 Added by Todd Strader 4 months ago
RE: RFC: DPI encapsulated Verilog instead of encryption
PSA: rr is amazing Todd Strader 07/25/2019 02:44 PM 2 Added by Todd Strader 5 months ago
RE: PSA: rr is amazing
One eval() method per clock domain ? Frederic Requin 07/21/2019 10:05 AM 1 Added by Wilson Snyder 5 months ago
RE: One eval() method per clock domain ?
Error on indexing the multiple dimensional array (MDA) Yu Sheng Lin 04/08/2019 02:52 AM 4 Added by Wilson Snyder 5 months ago
RE: Error on indexing the multiple dimensional array (MDA)
trying to run the tests Bryan Murdok 09/15/2018 10:12 PM 7 Added by Wilson Snyder 9 months ago
RE: trying to run the tests
detecting edges in an initial block Art. FR 03/02/2019 10:53 AM 1 Added by Wilson Snyder 9 months ago
RE: detecting edges in an initial block
Environment variable VERILATOR_GDB is not used. Yu Sheng Lin 02/12/2019 04:50 PM 1 Added by Wilson Snyder 10 months ago
RE: Environment variable VERILATOR_GDB is not used.
interface modport expression Edmond Cote 11/02/2015 06:44 PM 3 Added by Bob Kitchin 11 months ago
RE: interface modport expression
Multiple top modules for lint Kris Jeon 01/02/2019 09:48 AM 8 Added by Kris Jeon 11 months ago
RE: Multiple top modules for lint
std::abort and others in error handlers Michal Orsak 10/26/2018 10:04 PM 1 Added by Wilson Snyder about 1 year ago
RE: std::abort and others in error handlers
can verilator -E preserve comments? Robert Henry 10/25/2018 08:33 PM 1 Added by Wilson Snyder about 1 year ago
RE: can verilator -E preserve comments?
fix "fstapi.c" for MinGW HyungKi Jeong 10/12/2018 12:50 AM 1 Added by Wilson Snyder about 1 year ago
RE: fix "fstapi.c" for MinGW
A way to support LXT2 file format natively Yu Sheng Lin 08/12/2018 03:31 PM 14 Added by Sergi Granell about 1 year ago
RE: A way to support LXT2 file format natively
A problem with shared Vlvbound variables James Hanlon 09/07/2018 02:28 PM 2 Added by James Hanlon over 1 year ago
RE: A problem with shared Vlvbound variables
question about multithreaded execution feature. Marshal qiao 09/18/2016 07:20 AM 5 Added by Marshal qiao over 1 year ago
RE: question about multithreaded execution feature.
Multithreaded/multicore/GPU support Wilson Snyder 05/05/2012 03:25 PM 5 Added by Wilson Snyder over 1 year ago
RE: Multithreaded/multicore/GPU support
Verilator doesn't support UTF-8 formated verilog files. HyungKi Jeong 06/05/2018 06:11 AM 3 Added by Wilson Snyder over 1 year ago
RE: Verilator doesn't support UTF-8 formated verilog files.
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