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Issues

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# Status Priority Subject Assignee Updated
1318AskedReporterNormalIncorrect paths when compiling from Git06/08/2018 12:11 PM
1316ResolvedNormalLinear searches exposed by large design (v4.0)John Coiner06/12/2018 08:51 AM
1315NewNormalUsing an array in a function called from a parameter06/05/2018 02:17 AM
1314ConfirmedNormalBad scaling, if there are nasty forests of generate statementsJohn Coiner05/31/2018 11:25 PM
1307AskedReporterNormalCan not dump trace with CMAKE compiled SystemC libraryEnzo Chi05/09/2018 10:33 PM
1305ConfirmedNormalError messages do not contain hierarchical informationTodd Strader05/04/2018 10:38 AM
1303AssignedLowVCD Filter FilesStefan Wallentowitz05/19/2018 12:04 PM
1302AssignedLowDoxygen documentationStefan Wallentowitz04/19/2018 02:09 PM
1296FeatureNormalSystemVerilog logic array inside struct should warn on bad index03/30/2018 06:32 AM
1292ConfirmedNormalscr1 test suite: |-> and |=> operators are unsupported in assertions04/17/2018 02:50 PM
1289ConfirmedNormalscr1 test suite: string.hextoa is not implemented03/09/2018 05:02 PM
1288ConfirmedNormalscr1 test suite: In some cases mixed assignment to struct member fails03/10/2018 08:32 PM
1286ConfirmedNormalscr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks03/10/2018 04:21 AM
1282AssignedNormalFalse UNOPTFLAT warning when using 2 interfaces with the same name on different hierarchies, connected to each-other with wire03/04/2018 12:27 PM
1278ConfirmedNormalUnsupported LHS tristate construct: ARRAYSEL02/26/2018 09:05 AM
1276AskedReporterNormalvcd trace splits packed data type when it comes through a typedef03/09/2018 04:58 AM
1249AskedReporterNormalStruct initialisation with data type and member name is not supported in 3.916 12/14/2017 12:52 AM
1244ResolvedNormalV3Split not splittingJonas Kahnwald02/28/2018 12:01 PM
1222AskedReporterNormalVerilator behaviour of driving DUT inputs10/03/2017 11:12 AM
1221AskedReporterNormalVerilator is unfriendly to cross compiling verilated output. Simple fix.09/28/2017 10:23 PM
1185FeatureNormalSupport for interfaces in top level ports08/29/2017 02:54 AM
1184FeatureNormalVerilator doesn't detect multiple assignment11/19/2017 12:53 PM
1104FeatureNormalNo support for parameterized interface in module "signal" list.11/23/2017 05:24 PM
1096ConfirmedNormalUNOPT and UNOPTFLAT V3Split optimizations07/12/2017 02:14 AM
1052FeatureNormalLocalparam array can't be passed into parameter-called function04/07/2016 09:20 AM
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