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Issues

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# Status Priority Subject Assignee Updated
1467 Closed Normal Constant function evaluator incorrect on return of function var Wilson Snyder 06/16/2019 01:59 PM
1462 Closed Normal signal redeclaration is not reported Wilson Snyder 06/22/2019 04:50 PM
1449 Closed Low deferred assertion support Wilson Snyder 06/16/2019 01:58 PM
1443 Closed Normal Calling $display with real %t argument causes segfault in _vl_vsformat Wilson Snyder 06/16/2019 01:58 PM
1441 Closed Normal incorrect handling of strings in display and sformatf Wilson Snyder 06/16/2019 01:58 PM
1431 Closed Normal Multiple local variables with the same name ( __Vtable1_valid ) generated in a header file when using SystemVerilog interfaces in a certain situation Wilson Snyder 05/09/2019 01:38 AM
1426 Closed Normal enum logic[2:0] not generating enum in fst file Wilson Snyder 05/09/2019 01:38 AM
1424 Closed Normal Verilator does not complain about invalid parameter declaration Wilson Snyder 05/09/2019 07:03 AM
1423 Closed Normal 2 issues with unsized x/z constants Wilson Snyder 05/09/2019 01:37 AM
1422 NoFixNeeded Normal VPI hierarchy naming Wilson Snyder 06/29/2019 10:16 AM
1417 Closed Low FST regression tests fail instead of skip if fst2vcd isn't installed Wilson Snyder 05/09/2019 01:38 AM
1407 NotEnoughInfo Urgent facing a error for verilatedvcdsc Wilson Snyder 05/10/2019 12:29 AM
1406 Closed Low Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion in verilated.cpp in Visual Studio Wilson Snyder 03/24/2019 01:15 AM
1405 WillNotFix Normal Port defined as a net but used as a reg is not flagged as an error Wilson Snyder 03/11/2019 08:33 AM
1400 Closed Normal Bug: verilator sometimes fails to detect electrical short Wilson Snyder 03/24/2019 01:15 AM
1396 Closed Normal Verilator random number generated seeded with lrand48(), which isn't deterministic across platforms Wilson Snyder 03/24/2019 01:15 AM
1391 Closed Normal Trying to cast non-static DPI export functions to (void *) Wilson Snyder 01/28/2019 12:32 PM
1388 Closed Normal Circular typedef causes infinite loop Wilson Snyder 01/28/2019 12:32 PM
1387 Closed Normal Internal error when task is used to assign subscripted vector Wilson Snyder 01/28/2019 12:32 PM
1386 Closed Normal Reading free memory after unrolling a gen loop Wilson Snyder 01/28/2019 12:32 PM
1385 Closed Normal Uninitialized data written to dependency file, if executable is found from PATH Wilson Snyder 01/28/2019 12:32 PM
1384 Closed Normal File-extension language option not consistently applied Wilson Snyder 03/24/2019 01:15 AM
1383 Closed Normal Support SystemVerilog void casts & warn if not present Wilson Snyder 03/24/2019 01:15 AM
1381 Closed Normal "Duplicate declaration of cell" diagnostic with missing location Wilson Snyder 01/28/2019 12:32 PM
1380 Closed Normal Large numbers silently truncated Wilson Snyder 01/28/2019 12:32 PM
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