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Issues

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# Status Priority Subject Assignee Updated
851 Closed Normal Add more detailed statistics Jeremy Bennett 12/20/2014 09:52 PM
850 Feature Normal Find UNUSED and UNDRIVEN components in structs Jeremy Bennett 11/26/2014 10:03 PM
849 Closed Normal Missing header in VlcMain.cpp Jeremy Bennett 11/26/2014 09:47 PM
794 Closed Normal Small bug in t_vpi_get test Jeremy Bennett 06/27/2014 01:46 AM
678 Confirmed Normal Missing initial positive edge when using --x-initial-edge Jeremy Bennett 09/30/2013 05:57 PM
651 Closed Normal Different versions of GCC cause Verilator generated models to succeed or fail Jeremy Bennett 06/02/2013 06:54 PM
639 Closed Normal Small improvements to internals documentation Jeremy Bennett 04/28/2013 01:04 PM
613 Closed Normal Better gated clock support Jeremy Bennett 08/15/2013 12:46 PM
611 Closed Normal Improvements to UNOPTFLAT reporting Jeremy Bennett 03/09/2013 09:51 PM
610 Closed Normal DETECTARRAY error on packed structures Jeremy Bennett 03/09/2013 09:51 PM
605 Closed Normal bit-select with :+ and :- fails with packed structures Jeremy Bennett 01/18/2013 02:49 AM
604 Closed Normal -x-initial-edge breaks with logic bug fix Jeremy Bennett 01/17/2013 12:21 PM
580 Closed Normal --debug overrides preceding --dump-treei value Jeremy Bennett 12/01/2012 09:42 PM
578 NoFixNeeded Normal Short-circuit bitwise-AND and bitwise-OR (Verilog only) Jeremy Bennett 11/14/2012 02:30 AM
570 Closed Normal Triggering initial edge from X Jeremy Bennett 11/04/2012 12:25 AM
555 Closed Normal Tidy up DOT file output Jeremy Bennett 08/27/2012 11:03 PM
554 Closed Normal Updates to the internal documentation Jeremy Bennett 08/27/2012 04:04 PM
553 Closed Normal Corrections to two regression tests Jeremy Bennett 08/25/2012 04:05 PM
552 Closed Normal Tidy up .gitignore and MANIFEST.SKIP Jeremy Bennett 08/25/2012 11:52 AM
536 Closed Normal Regression test driver does not generate initial VCD values Jeremy Bennett 07/24/2012 10:49 PM
532 Closed Normal Support +systemverilogext+ Jeremy Bennett 12/01/2012 09:41 PM
530 Closed Normal Compiler error with GCC 4.7.0 Jeremy Bennett 07/31/2012 10:56 PM
515 Closed Normal Test for System Verilog enumeration methods Jeremy Bennett 05/21/2012 10:42 PM
497 Closed Normal More updates to the internal documentation Jeremy Bennett 04/26/2012 11:11 AM
492 Closed Normal Generate IF conditional does not correctly handle constant selections Jeremy Bennett 04/25/2012 10:17 PM
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