Issues: verilator/verilator
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Verilator performance issue
area: performance
Issue involves performance issues
status: asked reporter
Bug is waiting for reporter to answer a question
#4858
opened Jan 24, 2024 by
davidharrishmc
assert property with iff fails to compile
area: assertions
Issue involves assertions
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4848
opened Jan 21, 2024 by
udif
Segmentation fault in traceInit
status: asked reporter
Bug is waiting for reporter to answer a question
#4835
opened Jan 17, 2024 by
flaviens
No __en or __out variables declared for top level inout ports
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-non-IEEE
Request to add new feature, outside IEEE 1800
#4812
opened Jan 8, 2024 by
polmacanceart
Verilator $sscanf reads into array with a delay
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4811
opened Jan 7, 2024 by
davidharrishmc
Fix unpacked structure delayed references
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4804
opened Jan 5, 2024 by
futurehome
Virtual interface assign from class task generates no trace dumps and doesn't trigger assign statements
area: tracing
Issue involves tracing
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4780
opened Dec 24, 2023 by
jwoutersymatra
Fix generate ifs to allow sharing same dotted name
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4769
opened Dec 16, 2023 by
solomatnikov
Internal error with nested virtual interfaces/bind statements
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4767
opened Dec 15, 2023 by
eliasphanna
Combine function passes into single traversal
area: performance
Issue involves performance issues
status: discussion
Issue is waiting for discussions to resolve
#4737
opened Dec 3, 2023 by
gezalore
Support force/release on unpacked array
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4735
opened Dec 3, 2023 by
raghav-g13
Compilation Error when Trying to Print an Unpacked Array with ‘%p’
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4732
opened Dec 1, 2023 by
kdstrike
Double bug report: VCD corruption and optimization error for 5 optimization types
area: tracing
Issue involves tracing
status: asked reporter
Bug is waiting for reporter to answer a question
#4724
opened Nov 29, 2023 by
flaviens
Support struct on primary module ports
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-non-IEEE
Request to add new feature, outside IEEE 1800
#4716
opened Nov 23, 2023 by
Entwinedime
Wrong simulation result with adders and single-bit exclusive or gates
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
status: asked reporter
Bug is waiting for reporter to answer a question
#4709
opened Nov 20, 2023 by
flaviens
Support Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
std::randomize() with
status: blocked
#4706
opened Nov 20, 2023 by
muzafferkal
typedef within a class not found
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4705
opened Nov 19, 2023 by
muzafferkal
Support 2D dynamic array initialization
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4700
opened Nov 17, 2023 by
stevobailey
Add unsupported message when disable isn't underneath a begin with name
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4699
opened Nov 16, 2023 by
thesourcerer8
Reference module ports don't work when modules aren't inlined
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4698
opened Nov 16, 2023 by
RRozak
Fix false 'else' points in coverage
area: coverage
Issue involves coverage generation
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4691
opened Nov 12, 2023 by
gkamendje
Optimize redundant timestamps in trace files
area: tracing
Issue involves tracing
effort: hours
Expect this issue to require roughly hours of invested effort to resolve
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4686
opened Nov 12, 2023 by
wsnyder
Support unpacked structs in DPI-C calls
area: vpi/dpi/api
Issue involves VPI, DPI, or verilated.h interface API
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4679
opened Nov 10, 2023 by
mpriestleyidex
Combinational/Expression Coverage
status: discussion
Issue is waiting for discussions to resolve
#4677
opened Nov 8, 2023 by
rsammelson
Evasive malloc failure in some instances
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4674
opened Nov 7, 2023 by
flaviens
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