Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

# Status Priority Subject Assignee Updated
1372 Closed Normal XML output insufficiently qualified Wilson Snyder 01/28/2019 12:32 PM
1285 Closed Normal scr1 test suite: built-in system functions only work when the return value is assigned Wilson Snyder 03/17/2018 04:03 PM
1218 NoFixNeeded Normal module instance named clocking, expecting identifier 09/21/2017 05:56 PM
1165 Closed Normal $value$plusargs requires a string instead of an expression 05/31/2017 02:06 AM
1155 NoFixNeeded Normal verilog context free grammar 04/26/2017 11:16 AM
868 Closed Normal Trouble mixing older Verilog port syntax with SystemVerilog interfaces Wilson Snyder 02/13/2015 01:41 AM
863 Closed Low Cannot define real values in macros when using underscore Wilson Snyder 12/20/2014 09:53 PM
810 Closed Normal ommiting parameter keyword Wilson Snyder 09/21/2014 01:11 PM
780 Closed High Preprocessor incorrectly parses define arguments Derek Lockhart 06/11/2014 12:59 AM
749 Closed High Name of instance inside "for" loop clashes with name of an instance located outside of the loop scope Wilson Snyder 06/11/2014 12:56 AM
745 Closed Normal always @ ({signal1, signal2, etc}) triggers syntax error, unexpected '{' Wilson Snyder 05/11/2014 09:08 PM
741 Closed Normal Verilator 3.856 errors on reserved words as struct members Verilator 3.850 did not Wilson Snyder 05/11/2014 09:08 PM
657 NotEnoughInfo Normal Read Parmetarized Verilog File 08/13/2013 10:10 AM
550 Closed Normal Memory corruption when parsing modules with triangle dependancy 09/04/2012 12:15 AM
501 Closed Normal Real data type lost/Expected real input to RTOIS Wilson Snyder 07/31/2012 10:55 PM
443 Closed Low verilator hangs up on circular macro definition Wilson Snyder 03/08/2012 04:08 AM
404 Closed Normal space in always @(* ) causes internal error Wilson Snyder 10/25/2011 11:11 PM
380 Feature Normal Support of VHDL93 Sebastien Van Cauwenberghe 08/10/2011 06:49 AM
329 Closed Normal seg. fault on incorrect Verilog Wilson Snyder 04/06/2011 11:40 AM
326 Closed Normal vectored fufif1 primitive Wilson Snyder 04/06/2011 11:40 AM
306 Closed Normal (preprocessor) define propagates across files Wilson Snyder 12/02/2010 08:23 PM
291 Closed Low Verilator crashes on 'output wire foo = 0' in portlist Wilson Snyder 11/03/2010 01:26 AM
289 Closed Normal incorrect source file name in error message after include Wilson Snyder 10/26/2010 02:23 PM
205 Closed Normal Signal declarations in for loops don't work everywhere Byron Bradley 02/07/2010 12:42 PM
3 Closed Normal gate_instantiation .. name_of_gate_instance should allow range (1364-2001) Wilson Snyder 04/25/2008 03:27 PM
    (1-25/25)

    Also available in: Atom CSV