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Support interface in the top module when creating a library (--lib-create, --protect-lib, and --hierarchical)
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3275
opened Jan 8, 2022 by
yTakatsukasa
Internals: Improve tree syntax checks
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: maintenance
Internal maintenance task
#3264
opened Jan 2, 2022 by
wsnyder
1 of 4 tasks
Resolve width mismatch of biops
area: data-types
Issue involves data-types
#3245
opened Dec 11, 2021 by
yTakatsukasa
Support lint feature that checks naming rules
area: lint
Issue involves SystemVerilog lint checking
effort: days
Expect this issue to require roughly days of invested effort to resolve
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-non-IEEE
Request to add new feature, outside IEEE 1800
#3226
opened Dec 5, 2021 by
ghost
fscanf into structures generates invalid C++ code
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3224
opened Dec 3, 2021 by
adrienlemasle
Set the L2-name scope from the C++ instantiation
resolution: answered
Closed; only applies to questions which were answered
#3210
opened Nov 18, 2021 by
quark17
import-DPI with an open array for the packed dimension
area: vpi/dpi/api
Issue involves VPI, DPI, or verilated.h interface API
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#3198
opened Nov 12, 2021 by
quark17
No IData cast when shift items of array.
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3193
opened Nov 6, 2021 by
yanx21
Width of enum members with explicit value is not detected.
area: lint
Issue involves SystemVerilog lint checking
#3187
opened Oct 29, 2021 by
DaveMcEwan
Giving the SystemC module the same name as the top level verilog module using --preifx results in not compilable code
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3173
opened Oct 14, 2021 by
voertler
Initialization of parameter of instance with pattern
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3144
opened Sep 22, 2021 by
RRozak
Default --expand-limit setting may generate slower code.
area: performance
Issue involves performance issues
#3117
opened Sep 6, 2021 by
yanx21
Optimize redundant Vtemp assignments
area: performance
Issue involves performance issues
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3105
opened Aug 19, 2021 by
yanx21
Verilator does not follow the genblk naming scheme presented in the LRM
area: elaboration
Issue involves elaboration phase
effort: days
Expect this issue to require roughly days of invested effort to resolve
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#3100
opened Aug 17, 2021 by
alaindargelas
Add warning/error when method function return value not used
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3089
opened Aug 3, 2021 by
mballance
Module/etc never assigned a symbol entry
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3085
opened Jul 27, 2021 by
mateo-vm
Trace DPI import calls with --prof-threads
area: performance
Issue involves performance issues
area: usability
Issue involves general usability
effort: hours
Expect this issue to require roughly hours of invested effort to resolve
status: discussion
Issue is waiting for discussions to resolve
#3084
opened Jul 25, 2021 by
gezalore
Always_comb with IF statement, may not simulate correctly.
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3062
opened Jul 8, 2021 by
yanx21
Add error on illegal enum using struct packed base type
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3010
opened Jun 5, 2021 by
jeras
lint-only: no warning when reg type is used in output port connection
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#3003
opened Jun 3, 2021 by
it3q
Optimize bit operation combination
area: performance
Issue involves performance issues
effort: days
Expect this issue to require roughly days of invested effort to resolve
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#2993
opened May 31, 2021 by
flex-liu
The out-of-bounds part-select write behavior is inconsistent with IEEE
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#2984
opened May 27, 2021 by
Superchao-ai
Can't get the value that would be assigned in the next GEN-FOR iteration.
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#2983
opened May 27, 2021 by
yanx21
BLKSEQ missed when connecting module port to array
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#2973
opened May 19, 2021 by
Julian2n7000
UNOPTFLAT lint warning (for tree arbiter)
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#2969
opened May 18, 2021 by
rswarbrick
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