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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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295 Open 2,938 Closed
295 Open 2,938 Closed
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Issues list

Can't get the value that would be assigned in the next GEN-FOR iteration. area: wrong runtime result Issue involves an incorrect runtine result from Verilated model status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2983 opened May 27, 2021 by yanx21
7
BLKSEQ missed when connecting module port to array area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2973 opened May 19, 2021 by Julian2n7000
3
UNOPTFLAT lint warning (for tree arbiter) area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2969 opened May 18, 2021 by rswarbrick
3
Can we make verilated code more ccache-friendly? area: performance Issue involves performance issues
#2958 opened May 14, 2021 by rswarbrick
@gezalore
21
using unpacked array as a module port (and module parameter) status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2907 opened Apr 27, 2021 by jeras
3
Add lint error on multiple declarations of net and variable names area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2903 opened Apr 21, 2021 by albert-magyar
3
Support simple single-variable randomization effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2879 opened Apr 7, 2021 by agrobman
3
Verilator generates errors for unreachable generate/if/endgenerate code area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2866 opened Mar 30, 2021 by udif
4
Fix overzealous LATCH warning with procedure-local vars area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2862 opened Mar 28, 2021 by tsailer
@margej
11
Support feedthroughs/non-ANSI complex ports (IEEE 1800-2017 23.2.2.1) type: feature-IEEE Request to add new feature, described in IEEE 1800
#2844 opened Mar 18, 2021 by ganghuang
5
Compile error assigning to unpacked from packed array area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2843 opened Mar 18, 2021 by johnjohnlin
9
Feature Request: Black box for modules which allow to lint-just-in-time status: discussion Issue is waiting for discussions to resolve
#2835 opened Mar 14, 2021 by ToTamire
3
Address sanitizer upset on bit-select operations over-reading memory status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2819 opened Mar 5, 2021 by mytbk
3
Support VPI access to a multidimensional packed array area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2812 opened Feb 28, 2021 by Guillaume000000
4
Improve gated clock support in hierarhical verilation area: wrong runtime result Issue involves an incorrect runtine result from Verilated model status: discussion Issue is waiting for discussions to resolve type: feature-non-IEEE Request to add new feature, outside IEEE 1800
#2807 opened Feb 23, 2021 by yTakatsukasa
4
Support pin concat converting to 2D pattern assignment area: data-types Issue involves data-types status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2797 opened Feb 19, 2021 by zhuzhzh
1
Support runtime reference to cell/interface array area: elaboration Issue involves elaboration phase status: blocked Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2788 opened Feb 14, 2021 by mmatzev
1
Support typedef of parameterized structure in interface effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#2783 opened Feb 8, 2021 by zegervdv
2
generate for Can't find definition in dotted task/function area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2765 opened Jan 24, 2021 by KGHVerilator
5
Add a single line "lint_ignore" verilator comment area: lint Issue involves SystemVerilog lint checking type: feature-non-IEEE Request to add new feature, outside IEEE 1800
#2755 opened Jan 14, 2021 by phhorrein
8
Unpacked array of single bit seen as Net in VPI area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API
#2727 opened Dec 24, 2020 by phhorrein
1
2
Internal movement of V3Inst Dearray processing area: elaboration Issue involves elaboration phase effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: maintenance Internal maintenance task
#2675 opened Dec 6, 2020 by wsnyder
Support hashing signals to establish initial values status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-non-IEEE Request to add new feature, outside IEEE 1800
#2662 opened Dec 1, 2020 by wsnyder
Identically named interfaces across hierarchy confuses Verilator status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2656 opened Nov 25, 2020 by jedbian
3
Failure to link nested interfaces. area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#2649 opened Nov 18, 2020 by dgarau
6
ProTip! Updated in the last three days: updated:>2024-04-15.