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Issues

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# Status Priority Subject Assignee Updated
1475 Resolved Normal V3Hashed.cpp Called isIdentical on non-hashed nodes, from Gate dedupe() Wilson Snyder 08/04/2019 10:10 AM
1472 AskedReporter High Memory not updating in for loop 06/26/2019 10:50 PM
1467 Closed Normal Constant function evaluator incorrect on return of function var Wilson Snyder 06/16/2019 01:59 PM
1458 Closed Normal Dotted references to type parameters do not have the correct size Todd Strader 06/16/2019 01:59 PM
1455 Closed Low Multi-threaded verilated simulation on single-core Stefan Wallentowitz 06/16/2019 01:59 PM
1444 Closed Normal Invalid xml output generated when code contains functions with string arguments Kanad Kanhere 06/16/2019 01:59 PM
1441 Closed Normal incorrect handling of strings in display and sformatf Wilson Snyder 06/16/2019 01:58 PM
1412 Closed Normal Verilator generates calls to an undefined function named: VL_SHIFTL_QQW Larry Lee 05/09/2019 01:37 AM
1409 NoFixNeeded Normal Incorrect Result of Cascading Module Using Generate Statement 03/15/2019 11:12 AM
1399 NoFixNeeded Normal x-assign and x-initial 'unique' setting appears not to work 03/02/2019 01:19 AM
1377 NotEnoughInfo Normal Segmentation Fault when tracing is enabled Wilson Snyder 03/10/2019 06:21 PM
1376 Closed Normal Incorrect array contents in FST and LXT2 output formats Wilson Snyder 01/28/2019 12:32 PM
1373 Feature Normal Cannot write to top-level tristate ports 12/06/2018 05:10 PM
1327 Closed Normal Strange initialisation behaviour with "VinpClk" cloned clock variables Wilson Snyder 09/16/2018 09:28 PM
1307 NotEnoughInfo Normal Can not dump trace with CMAKE compiled SystemC library Enzo Chi 05/24/2019 08:03 AM
1226 Closed Normal -E repeats output Wilson Snyder 10/14/2017 08:22 PM
1172 Closed Normal Incorrect result for packed array with non-zero LSB typedef Wilson Snyder 06/22/2017 10:37 PM
1150 Closed Normal wreal implicit assignments don't reevaluate Wilson Snyder 04/02/2017 12:52 PM
1139 Closed Normal elaboration time sformatf does not work Johan Bjork 04/02/2017 12:52 PM
1121 NotEnoughInfo Normal Simulation errors with clock bus 12/17/2017 11:01 PM
1042 NotEnoughInfo Normal assignment to a packed array variable formed from a concatenation 04/02/2017 12:57 PM
1037 Closed Normal Verilator truncates statement incorrectly for pattern assignments Wilson Snyder 03/02/2016 12:16 AM
1036 Confirmed Normal Reset fails to respond when driven from vector containing clock enable 02/24/2016 02:42 PM
1027 Confirmed Normal Partly out of range part-select gives wrong runtime result 02/10/2016 07:30 PM
1024 NoFixNeeded Normal Test fails with certain optimizations disabled 01/21/2016 03:27 AM
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