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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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299 Open 2,943 Closed
299 Open 2,943 Closed
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Issues list

Support cross hierarchy assignment to input-only status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3709 opened Oct 26, 2022 by balanx
6
$ungetclvalue cast should give error area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3705 opened Oct 24, 2022 by jeras
2
Self-trigger by delay area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3697 opened Oct 20, 2022 by kbieganski
Support for interfaces as top level ports status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3655 opened Oct 4, 2022 by kkanhere
1
Support of unknown values (X) in design effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800
#3645 opened Sep 27, 2022 by suzizecat
8
Support Public SystemVerilog Enum Using `verilator_config status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-non-IEEE Request to add new feature, outside IEEE 1800
#3618 opened Sep 12, 2022 by bobnewgard
3
Support OVM (@v2.1.2) status: blocked Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned'
#3611 opened Sep 11, 2022 by benjaminmordaunt
3
Assignment pattern key not supported/understood when key is actually a localparam area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3605 opened Sep 8, 2022 by shesselba
1
Case eq statement doesn't work when net is compared with z status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3590 opened Sep 2, 2022 by RRozak
12
Superfluous extra domains for vars written in suspendables area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3564 opened Aug 19, 2022 by kbieganski
Fork locals passed as arguments to fork area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3563 opened Aug 19, 2022 by kbieganski
Continuous assignment with delay UNOPTFLAT area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3562 opened Aug 19, 2022 by kbieganski
Event controls in class methods area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3561 opened Aug 19, 2022 by kbieganski
always_comb does not warn about latch status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3474 opened Jun 27, 2022 by pinkcatfly
5
Package misidentified as dead, causing Internal Error, Broken link in node->dtypep() status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3467 opened Jun 15, 2022 by supleed2
2
Support inout inside SystemVerilog interface effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3466 opened Jun 13, 2022 by nickelpro
3
Parallelization of Verilator code area: performance Issue involves performance issues status: discussion Issue is waiting for discussions to resolve
#3458 opened May 31, 2022 by mglb
1
Verilating t/t_merge_cond_blowup.pl with --vltmt takes too long. area: performance Issue involves performance issues area: scheduling Issue involves scheduling/ordering of events area: usability Issue involves general usability status: discussion Issue is waiting for discussions to resolve
#3450 opened May 27, 2022 by gezalore
1
typedef derived from type defined inside interface status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3441 opened May 22, 2022 by solomatnikov
4
Support localparam integer array slicing status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#3433 opened May 17, 2022 by michael-platzer
2
Support callback handlers instead of verilated.cpp ifdefs area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API
#3423 opened May 15, 2022 by wsnyder
Encapsulate verilated models independent of each other and the process status: discussion Issue is waiting for discussions to resolve
#3419 opened May 15, 2022 by gezalore
5
SystemVerilog size (tick) operator with expressions area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3417 opened May 15, 2022 by Blutyek
Many string operations cause compile time hang status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3415 opened May 14, 2022 by shareefj
15
Side effect function inside unsatisfied if condition get executed area: wrong runtime result Issue involves an incorrect runtine result from Verilated model status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#3395 opened Apr 22, 2022 by weisrc
19
ProTip! Follow long discussions with comments:>50.