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# Status Priority Subject Assignee Updated
1620 Closed Normal Dotted function reference causes Internal Error Wilson Snyder 12/08/2019 01:11 PM
1616 Closed Normal Intenal Error of "Multiple root modules" happens if one of sub modules is not inlined when creating a protect lib. Todd Strader 12/02/2019 01:35 PM
1614 Closed Normal Multiple label redefinition/parsing issue for constant functions used in computational loops Wilson Snyder 12/08/2019 01:11 PM
1604 Closed Normal Unknown node in split color() map on empty if Wilson Snyder 12/08/2019 01:13 PM
1574 Closed Normal Fuzzer: Hang on inifinite define expansion Wilson Snyder 10/29/2019 07:04 PM
1555 NoFixNeeded Normal Asynchronous reset logic is inconsistent with rtl Todd Strader 11/05/2019 03:10 AM
1554 AskedReporter Normal There is a problem when Handling variables forced type conversion Todd Strader 11/05/2019 03:10 AM
1465 Closed Normal --savable generates invalid c++ for some packed arrays Alex Chadwick 06/16/2019 01:59 PM
1456 Closed Normal sameHash error on type parameters after 4.014 06/16/2019 01:59 PM
1443 Closed Normal Calling $display with real %t argument causes segfault in _vl_vsformat Wilson Snyder 06/16/2019 01:58 PM
1431 Closed Normal Multiple local variables with the same name ( __Vtable1_valid ) generated in a header file when using SystemVerilog interfaces in a certain situation Wilson Snyder 05/09/2019 01:38 AM
1430 AskedReporter Normal Broken node on indexed interface modport Wilson Snyder 05/22/2019 02:06 AM
1415 Closed Normal Verilator generates calls to an undefined function named: VL_SHIFTR_QQW Larry Lee 05/09/2019 01:37 AM
1391 Closed Normal Trying to cast non-static DPI export functions to (void *) Wilson Snyder 01/28/2019 12:32 PM
1387 Closed Normal Internal error when task is used to assign subscripted vector Wilson Snyder 01/28/2019 12:32 PM
1386 Closed Normal Reading free memory after unrolling a gen loop Wilson Snyder 01/28/2019 12:32 PM
1385 Closed Normal Uninitialized data written to dependency file, if executable is found from PATH Wilson Snyder 01/28/2019 12:32 PM
1381 Closed Normal "Duplicate declaration of cell" diagnostic with missing location Wilson Snyder 01/28/2019 12:32 PM
1364 Closed Low Verilator hangs in malloc() when assignment pattern key is not found Wilson Snyder 12/01/2018 08:17 PM
1347 Closed Normal Duplicate declaration on generate tristate UDP Wilson Snyder 09/16/2018 09:28 PM
1345 Closed Normal String conditional operation gives compile error Wilson Snyder 09/16/2018 09:28 PM
1330 Closed Normal Broken link error when inlining functions under while loops Wilson Snyder 08/22/2018 10:48 PM
1297 Duplicate Low 1 Bit signed values Wilson Snyder 04/01/2018 11:52 AM
1286 Confirmed Normal scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks 03/10/2018 04:21 AM
1274 Closed Normal Pullup / Pulldown on arrays causes internal crash Wilson Snyder 03/17/2018 04:03 PM
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