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Mac OS missing FlexLexer.h
status: assigned
Issue is assigned to someone to work on
#4970
opened Mar 12, 2024 by
ct-clmsn
Unexpected Significant Performance Degradation on Movement of Code
status: discussion
Issue is waiting for discussions to resolve
#4967
opened Mar 12, 2024 by
Karl-Han
Optimization for Conditional Statement
status: asked reporter
Bug is waiting for reporter to answer a question
#4964
opened Mar 11, 2024 by
europe2024
Why do we use TSP sort for variable ordering?
status: discussion
Issue is waiting for discussions to resolve
#4960
opened Mar 10, 2024 by
gezalore
Splitting heavy trace cpp files when --trace-max-array 131072 is used
area: performance
Issue involves performance issues
area: tracing
Issue involves tracing
#4948
opened Mar 7, 2024 by
alexeikom
verilator-config.cmake errors out when CMAKE_CXX_COMPILER_ID not defined before finding the verilator package.
area: configure/compiling
Issue involves configuring or compilating Verilator itself
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4939
opened Mar 1, 2024 by
phelter
Compilation error on extern function that returns parametrized class
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4924
opened Feb 25, 2024 by
esynr3z
Cell parameters lost when upper module used with default and non-default parameters
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4920
opened Feb 23, 2024 by
JosseVanDelm
Verilator public_on/off requires at least one individually marked wire
area: vpi/dpi/api
Issue involves VPI, DPI, or verilated.h interface API
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4916
opened Feb 22, 2024 by
AndrewNolte
Getting a module parameter using scope resolution operator
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4890
opened Feb 11, 2024 by
ba-sc
Support EVCD $dumpports
area: tracing
Issue involves tracing
effort: days
Expect this issue to require roughly days of invested effort to resolve
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4882
opened Feb 6, 2024 by
franout
Fatal error on split variable when tracing is enabled
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4871
opened Feb 2, 2024 by
adrienlemasle
Verilator performance issue
area: performance
Issue involves performance issues
status: asked reporter
Bug is waiting for reporter to answer a question
#4858
opened Jan 24, 2024 by
davidharrishmc
assert property with iff fails to compile
area: assertions
Issue involves assertions
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4848
opened Jan 21, 2024 by
udif
Verilator $sscanf reads into array with a delay
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4811
opened Jan 7, 2024 by
davidharrishmc
Fix unpacked structure delayed references
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4804
opened Jan 5, 2024 by
futurehome
Virtual interface assign from class task generates no trace dumps and doesn't trigger assign statements
area: tracing
Issue involves tracing
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4780
opened Dec 24, 2023 by
jwoutersymatra
Fix generate ifs to allow sharing same dotted name
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4769
opened Dec 16, 2023 by
solomatnikov
Internal error with nested virtual interfaces/bind statements
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4767
opened Dec 15, 2023 by
eliasphanna
Combine function passes into single traversal
area: performance
Issue involves performance issues
status: discussion
Issue is waiting for discussions to resolve
#4737
opened Dec 3, 2023 by
gezalore
Support force/release on unpacked array
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4735
opened Dec 3, 2023 by
raghav-g13
Compilation Error when Trying to Print an Unpacked Array with ‘%p’
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4732
opened Dec 1, 2023 by
kdstrike
Support struct on primary module ports
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-non-IEEE
Request to add new feature, outside IEEE 1800
#4716
opened Nov 23, 2023 by
Entwinedime
Wrong simulation result with adders and single-bit exclusive or gates
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
status: asked reporter
Bug is waiting for reporter to answer a question
#4709
opened Nov 20, 2023 by
flaviens
Support Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
std::randomize() with
status: blocked
#4706
opened Nov 20, 2023 by
muzafferkal
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