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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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291 Open 2,938 Closed
291 Open 2,938 Closed
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Issues list

verilator-config.cmake errors out when CMAKE_CXX_COMPILER_ID not defined before finding the verilator package. area: configure/compiling Issue involves configuring or compilating Verilator itself status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4939 opened Mar 1, 2024 by phelter
1
Compilation error on extern function that returns parametrized class area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4924 opened Feb 25, 2024 by esynr3z
5
Cell parameters lost when upper module used with default and non-default parameters area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4920 opened Feb 23, 2024 by JosseVanDelm
2
Verilator public_on/off requires at least one individually marked wire area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4916 opened Feb 22, 2024 by AndrewNolte
Getting a module parameter using scope resolution operator area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4890 opened Feb 11, 2024 by ba-sc
1
6
Support EVCD $dumpports area: tracing Issue involves tracing effort: days Expect this issue to require roughly days of invested effort to resolve status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4882 opened Feb 6, 2024 by franout
4
Fatal error on split variable when tracing is enabled status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4871 opened Feb 2, 2024 by adrienlemasle
4
Verilator performance issue area: performance Issue involves performance issues status: asked reporter Bug is waiting for reporter to answer a question
#4858 opened Jan 24, 2024 by davidharrishmc
11
assert property with iff fails to compile area: assertions Issue involves assertions status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4848 opened Jan 21, 2024 by udif
1
Verilator $sscanf reads into array with a delay status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4811 opened Jan 7, 2024 by davidharrishmc
3
Fix unpacked structure delayed references status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4804 opened Jan 5, 2024 by futurehome
3
Virtual interface assign from class task generates no trace dumps and doesn't trigger assign statements area: tracing Issue involves tracing status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4780 opened Dec 24, 2023 by jwoutersymatra
3
Fix generate ifs to allow sharing same dotted name area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4769 opened Dec 16, 2023 by solomatnikov
4
Internal error with nested virtual interfaces/bind statements area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4767 opened Dec 15, 2023 by eliasphanna
4
Combine function passes into single traversal area: performance Issue involves performance issues status: discussion Issue is waiting for discussions to resolve
#4737 opened Dec 3, 2023 by gezalore
3
Support force/release on unpacked array type: feature-IEEE Request to add new feature, described in IEEE 1800
#4735 opened Dec 3, 2023 by raghav-g13
6
Compilation Error when Trying to Print an Unpacked Array with ‘%p’ status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4732 opened Dec 1, 2023 by kdstrike
3
Support struct on primary module ports area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-non-IEEE Request to add new feature, outside IEEE 1800
#4716 opened Nov 23, 2023 by Entwinedime
3
Wrong simulation result with adders and single-bit exclusive or gates area: wrong runtime result Issue involves an incorrect runtine result from Verilated model status: asked reporter Bug is waiting for reporter to answer a question
#4709 opened Nov 20, 2023 by flaviens
3
Support std::randomize() with status: blocked Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4706 opened Nov 20, 2023 by muzafferkal
1
typedef within a class not found area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4705 opened Nov 19, 2023 by muzafferkal
2
Support 2D dynamic array initialization area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4700 opened Nov 17, 2023 by stevobailey
9
Add unsupported message when disable isn't underneath a begin with name area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4699 opened Nov 16, 2023 by thesourcerer8
3
Reference module ports don't work when modules aren't inlined status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4698 opened Nov 16, 2023 by RRozak
1
Fix false 'else' points in coverage area: coverage Issue involves coverage generation status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4691 opened Nov 12, 2023 by gkamendje
21
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