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# Status Priority Subject Assignee Updated
1366 AskedReporter Normal Large increase in design header file with threads and tracing 11/29/2018 11:13 PM
1483 Assigned Normal Make verilator_ext_tests head-to-head Todd Strader 08/04/2019 02:16 AM
1472 AskedReporter High Memory not updating in for loop 06/26/2019 10:50 PM
678 Confirmed Normal Missing initial positive edge when using --x-initial-edge Jeremy Bennett 09/30/2013 05:57 PM
533 Feature Low Missing width warning when part of a bus is compared 07/20/2012 03:27 PM
1487 Resolved Normal New WIDTH warnings on genvars Todd Strader 08/12/2019 08:17 PM
1104 Feature Normal No support for parameterized interface in module "signal" list. 11/23/2017 05:24 PM
629 Feature Low Non-vector timing loop warning 03/16/2013 12:33 AM
1027 Confirmed Normal Partly out of range part-select gives wrong runtime result 02/10/2016 07:30 PM
1489 New Normal Python support for Verilated designs Maarten De Braekeleer 08/14/2019 08:03 PM
1435 Resolved Normal Report column numbers and source text in error messages 07/15/2019 01:47 AM
1036 Confirmed Normal Reset fails to respond when driven from vector containing clock enable 02/24/2016 02:42 PM
1288 Confirmed Normal scr1 test suite: In some cases mixed assignment to struct member fails 03/10/2018 08:32 PM
1286 Confirmed Normal scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks 03/10/2018 04:21 AM
1292 Feature Normal scr1 test suite: |-> and |=> operators are unsupported in assertions 10/05/2018 01:01 AM
544 Feature Normal Support associative arrays 01/25/2019 12:20 AM
377 Feature Normal Support classes and methods 02/06/2016 11:16 PM
379 Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
726 Feature Normal Support enum type checking lint checks 03/25/2014 12:27 AM
860 Feature Low Support for /*verilator public*/ on SV structs too? 12/19/2014 11:17 PM
1185 Feature Normal Support for interfaces in top level ports 08/29/2017 02:54 AM
1454 Feature Normal Support for loop index into generated arrays 06/04/2019 11:05 AM
528 Feature Normal Support for reserved words weak0 and weak1 11/03/2012 12:04 PM
784 Feature Normal Support for SystemVerilog coverage 06/10/2014 02:00 AM
235 Feature Normal Support fork-joins and time delays 04/07/2010 01:27 PM
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