• Sign in
• Register

Search:

Issues

• View all issues
• Summary

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.

---

Filters

Add filter   Status Tracker Priority Author Assignee Target version Category Subject Description Estimated time % Done IssueAssignee's roleCreated Updated ClosedRelated to Duplicates Duplicated by Blocks Blocked by Precedes Follows Copied to Copied from Parent task Subtasks

Options

Columns	Available Columns Project Tracker Parent task Author Category Target version Estimated time Total estimated time % Done Created Closed Related issues Selected Columns Status Priority Subject Assignee Updated
Group results by	Project Tracker Status Priority Author Assignee Category Target version % Done
Show	Description
Totals	Estimated time

Apply Clear

	#	Status	Priority	Subject	Assignee	Updated
	1278	Confirmed	Normal	Unsupported LHS tristate construct: ARRAYSEL		02/26/2018 09:05 AM
	1104	Feature	Normal	No support for parameterized interface in module "signal" list.		11/23/2017 05:24 PM
	365	Feature	Normal	bidrectional arrays not supported as module ports		11/23/2017 04:45 PM
	1011	Confirmed	Normal	Can't reference interface functions inside of generate blocks		11/19/2017 12:56 PM
	1008	Confirmed	Normal	Incorrect results with partially out-of-bounds part select (re-opened)		11/19/2017 12:54 PM
	1184	Feature	Normal	Verilator doesn't detect multiple assignment		11/19/2017 12:53 PM
	1185	Feature	Normal	Support for interfaces in top level ports		08/29/2017 02:54 AM
	1096	Confirmed	Normal	UNOPT and UNOPTFLAT V3Split optimizations		07/12/2017 02:14 AM
	63	Feature	Normal	False Signal unoptimizable: circular logic warning		05/27/2016 10:14 PM
	1052	Feature	Normal	Localparam array can't be passed into parameter-called function		04/07/2016 09:20 AM
	1036	Confirmed	Normal	Reset fails to respond when driven from vector containing clock enable		02/24/2016 02:42 PM
	1027	Confirmed	Normal	Partly out of range part-select gives wrong runtime result		02/10/2016 07:30 PM
	377	Feature	Normal	Support classes and methods		02/06/2016 11:16 PM
	860	Feature	Low	Support for /*verilator public*/ on SV structs too?		12/19/2014 11:17 PM
	850	Feature	Normal	Find UNUSED and UNDRIVEN components in structs	Jeremy Bennett	11/26/2014 10:03 PM
	821	Feature	Normal	Is an indexed element into a parameter array a constant?		09/21/2014 12:53 PM
	792	Confirmed	Normal	Incorrect handling of index out of declared bound on multi-dim packed array		06/30/2014 07:34 AM
	784	Feature	Normal	Support for SystemVerilog coverage		06/10/2014 02:00 AM
	757	Feature	Normal	Verilator handling of combo always block		05/02/2014 12:40 PM
	726	Feature	Normal	Support enum type checking lint checks		03/25/2014 12:27 AM
	697	Feature	Normal	Support net aliasing		11/07/2013 07:22 PM
	678	Confirmed	Normal	Missing initial positive edge when using --x-initial-edge	Jeremy Bennett	09/30/2013 05:57 PM
	662	Confirmed	Normal	Clock gated signals not synchronised if used as a logical input		07/03/2013 12:39 AM
	629	Feature	Low	Non-vector timing loop warning		03/16/2013 12:33 AM
	593	Feature	Low	Support running make and creating top C file		01/15/2013 12:20 PM

• « Previous
• 1
• 2
• 3
• Next »

(26-50/71) Per page: 25, 100

Also available in: Atom CSV