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# Status Priority Subject Assignee Updated
485 Feature Low verilator does not detect if block name is used twice 04/19/2012 09:46 PM
468 Feature Low Support primitive instantiations 04/25/2012 12:43 AM
449 Confirmed Normal Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error Wilson Snyder 03/07/2012 02:09 PM
408 Confirmed Low verilator generates incorrect C++ code when genvar is used incorrectly 03/10/2012 07:09 AM
385 Feature Low Dpi exported tasks with array inputs don't compile. Wilson Snyder 07/15/2012 03:19 PM
380 Feature Normal Support of VHDL93 Sebastien Van Cauwenberghe 08/10/2011 06:49 AM
379 Feature Normal Support dynamic memory new and delete 03/02/2012 11:42 PM
378 Feature Normal Support properties and assertions 03/02/2012 11:42 PM
377 Feature Normal Support classes and methods 02/06/2016 11:16 PM
366 Feature Normal Support sensitivity of arrayed variables 07/21/2011 11:31 AM
365 Feature Normal bidrectional arrays not supported as module ports 11/23/2017 04:45 PM
364 Feature Low blocking & non-blocking assigns -- verilator issues error when no logical conflict exists Wilson Snyder 06/14/2019 11:17 PM
236 Feature Normal Support real event loop 04/07/2010 01:26 PM
235 Feature Normal Support fork-joins and time delays 04/07/2010 01:27 PM
234 Feature Normal Support time and `timescales 04/07/2010 01:27 PM
225 Feature Normal hierarchical compilation of designs for scalability 03/17/2010 08:14 PM
63 Feature Normal False Signal unoptimizable: circular logic warning 05/27/2016 10:14 PM
50 Feature Normal Clock gating support? 10/28/2009 01:51 PM
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