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# Status Priority Subject Assignee Updated
365 Feature Normal bidrectional arrays not supported as module ports 11/23/2017 04:45 PM
236 Feature Normal Support real event loop 04/07/2010 01:26 PM
235 Feature Normal Support fork-joins and time delays 04/07/2010 01:27 PM
234 Feature Normal Support time and `timescales 04/07/2010 01:27 PM
225 Feature Normal hierarchical compilation of designs for scalability 03/17/2010 08:14 PM
63 Feature Normal False Signal unoptimizable: circular logic warning 05/27/2016 10:14 PM
50 Feature Normal Clock gating support? 10/28/2009 01:51 PM
850 Feature Normal Find UNUSED and UNDRIVEN components in structs Jeremy Bennett 11/26/2014 10:03 PM
678 Confirmed Normal Missing initial positive edge when using --x-initial-edge Jeremy Bennett 09/30/2013 05:57 PM
487 Feature Normal Support short-circuiting of bitswise AND and OR Jeremy Bennett 11/14/2012 08:06 PM
1314 Confirmed Normal Bad scaling, if there are nasty forests of generate statements John Coiner 05/31/2018 11:25 PM
1363 AskedReporter Low CMake and Python support Patrick Stewart 04/28/2019 11:55 PM
380 Feature Normal Support of VHDL93 Sebastien Van Cauwenberghe 08/10/2011 06:49 AM
1470 Feature Low VPI systemtf Stefan Wallentowitz 06/20/2019 02:07 PM
1305 Confirmed Normal Error messages do not contain hierarchical information Todd Strader 07/10/2019 09:58 PM
1442 Resolved Normal Enum value not made sized when enum sized Wilson Snyder 07/06/2019 08:27 PM
1430 AskedReporter Normal Broken node on indexed interface modport Wilson Snyder 05/22/2019 02:06 AM
449 Confirmed Normal Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error Wilson Snyder 03/07/2012 02:09 PM
364 Feature Low blocking & non-blocking assigns -- verilator issues error when no logical conflict exists Wilson Snyder 06/14/2019 11:17 PM
(51-69/69) Per page: 25, 100

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