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# Status Priority Subject Assignee Updated
1305 Confirmed Normal Error messages do not contain hierarchical information Todd Strader 04/23/2019 05:29 PM
1288 Confirmed Normal scr1 test suite: In some cases mixed assignment to struct member fails 03/10/2018 08:32 PM
1286 Confirmed Normal scr1 test suite: processing passes get stuck, and allocate huge amounts of system RAM when verilog contains memory blocks 03/10/2018 04:21 AM
1278 Confirmed Normal Unsupported LHS tristate construct: ARRAYSEL 02/26/2018 09:05 AM
1096 Confirmed Normal UNOPT and UNOPTFLAT V3Split optimizations 07/12/2017 02:14 AM
1036 Confirmed Normal Reset fails to respond when driven from vector containing clock enable 02/24/2016 02:42 PM
1027 Confirmed Normal Partly out of range part-select gives wrong runtime result 02/10/2016 07:30 PM
1011 Confirmed Normal Can't reference interface functions inside of generate blocks 11/19/2017 12:56 PM
1008 Confirmed Normal Incorrect results with partially out-of-bounds part select (re-opened) 11/19/2017 12:54 PM
792 Confirmed Normal Incorrect handling of index out of declared bound on multi-dim packed array 06/30/2014 07:34 AM
678 Confirmed Normal Missing initial positive edge when using --x-initial-edge Jeremy Bennett 09/30/2013 05:57 PM
662 Confirmed Normal Clock gated signals not synchronised if used as a logical input 07/03/2013 12:39 AM
648 Confirmed Normal Error-BLKANDNBLK with nested modules in generate block 01/26/2019 04:28 AM
449 Confirmed Normal Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error Wilson Snyder 03/07/2012 02:09 PM
408 Confirmed Low verilator generates incorrect C++ code when genvar is used incorrectly 03/10/2012 07:09 AM
1282 Assigned Normal False UNOPTFLAT warning when using 2 interfaces with the same name on different hierarchies, connected to each-other with wire 03/04/2018 12:27 PM
1417 Resolved Low FST regression tests fail instead of skip if fst2vcd isn't installed Wilson Snyder 04/11/2019 12:52 AM
1415 Resolved Normal Verilator generates calls to an undefined function named: VL_SHIFTR_QQW Larry Lee 04/06/2019 01:20 AM
1413 Resolved Normal Wrong printf/scanf format specifiers used for MinGW targets Sergey Kvachonok 04/02/2019 10:25 PM
1412 Resolved Normal Verilator generates calls to an undefined function named: VL_SHIFTL_QQW Larry Lee 03/29/2019 12:20 AM
1411 Resolved Low # comments support in .mem files Frederic Requin 03/27/2019 11:40 AM
(51-71/71) Per page: 25, 100

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