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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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295 Open 2,938 Closed
295 Open 2,938 Closed
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Issues list

Fix UVM assignment of event data types area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4468 opened Sep 9, 2023 by wsnyder
1
wait(event) causes compile error rather than parse error area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4457 opened Sep 6, 2023 by jwoutersymatra
3
Systemverilog repeat loop (counter) lifetime error status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4451 opened Aug 31, 2023 by jwoutersymatra
3
Fix function_fork_valid regression with unknown type area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4449 opened Aug 30, 2023 by wsnyder
Support sequence status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4425 opened Aug 17, 2023 by Divya2030
2
--x-initial-edge triggers unwanted edge on first model eval area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4424 opened Aug 16, 2023 by Dolu1990
7
Support --lib-create option with --timing area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-non-IEEE Request to add new feature, outside IEEE 1800
#4410 opened Aug 9, 2023 by TarasSmarkutskyi
4
$monitor prints intermediate values during simulation deltas area: wrong runtime result Issue involves an incorrect runtine result from Verilated model effort: hours Expect this issue to require roughly hours of invested effort to resolve good first issue Good for newcomers status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4400 opened Jul 31, 2023 by 0-issue
1
Unlinked when getting bit width of type defined in parameterized class area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4391 opened Jul 27, 2023 by em2machine
5
BLKANDBLK error on SV queue area: elaboration Issue involves elaboration phase effort: days Expect this issue to require roughly days of invested effort to resolve good first issue Good for newcomers status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4373 opened Jul 19, 2023 by shareefj
2
$strobe and $monitor fail inside of task and with task output as argument status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4369 opened Jul 17, 2023 by mczyz-antmicro
4
Fix handling of clocks embedded in SV structs area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4363 opened Jul 13, 2023 by em2machine
1
Warning message for CASEINCOMPLETE generated in 5.002 does not occur in 5.012 area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4357 opened Jul 12, 2023 by calebofearth
3
Unsupported: Strength specifier on this gate type status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4340 opened Jul 5, 2023 by M0stafaRady
1
%Error-ASSIGNIN: ... Assigning to input/const variable: status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4334 opened Jul 3, 2023 by ylevhari
5
SV class vif sampling does not work status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4322 opened Jun 27, 2023 by svenka3
2
Virtual interface & clocking block leads to internal error status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4315 opened Jun 26, 2023 by svenka3
FAQ: How to register for announcements
#4298 opened Jun 17, 2023 by wsnyder
Some of type-related information seems unclear/misleading status: discussion Issue is waiting for discussions to resolve
#4293 opened Jun 13, 2023 by kboronski-ant
1
Support virtual interface parameterization status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4286 opened Jun 10, 2023 by jeras
9
Support unpacked struct elaboration parameters area: data-types Issue involves data-types status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4285 opened Jun 10, 2023 by jeras
2
How to properly create a working bidir pad for use with verilator. status: discussion Issue is waiting for discussions to resolve
#4278 opened Jun 7, 2023 by phelter
5
Support ##0 cycle delays area: assertions Issue involves assertions status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
#4263 opened Jun 2, 2023 by amykyta3
4
Non-equivalent library generation status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4242 opened May 28, 2023 by Phantom1003
3
Why the initial statement of a for loop is not seen outside of the loop? area: wrong runtime result Issue involves an incorrect runtine result from Verilated model good first issue Good for newcomers status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4237 opened May 26, 2023 by vicencb
5
ProTip! Exclude everything labeled bug with -label:bug.